PowerTrench MOSFET. FDG6317NZ Datasheet

FDG6317NZ Datasheet PDF, Equivalent


Part Number

FDG6317NZ

Description

Dual 20v N-Channel PowerTrench MOSFET

Manufacture

Fairchild Semiconductor

Total Page 5 Pages
PDF Download
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FDG6317NZ Datasheet
January 2004
FDG6317NZ
Dual 20v N-Channel PowerTrench® MOSFET
General Description
This dual N-Channel MOSFET has been designed
specifically to improve the overall efficiency of DC/DC
converters using either synchronous or conventional
switching PWM controllers. It has been optimized use
in small switching regulators, providing an extremely
low RDS(ON) and gate charge (QG) in a small package.
Applications
DC/DC converter
Power management
Loadswitch
Features
0.7 A, 20 V.
RDS(ON) = 400 m@ VGS = 4.5 V
RDS(ON) = 550 m@ VGS = 2.5 V
ESD protection diode (note 3)
Low gate charge
High performance trench technology for extremely
low RDS(ON)
Compact industry standard SC70-6 surface mount
package
S
G
D
Pin 1
D
G
S
SC70-6
The pinouts are symmetrical; pin 1 and pin 4 are interchangeable.
Absolute Maximum Ratings TA=25oC unless otherwise noted
Symbol
Parameter
VDSS
VGSS
ID
Drain-Source Voltage
Gate-Source Voltage
Drain Current – Continuous
– Pulsed
(Note 1)
PD
TJ, TSTG
Power Dissipation for Single Operation
(Note 1)
Operating and Storage Junction Temperature Range
Thermal Characteristics
RθJA Thermal Resistance, Junction-to-Ambient
(Note 1)
Package Marking and Ordering Information
Device Marking
Device
Reel Size
.67
FDG6317NZ
7’’
©2004 Fairchild Semiconductor Corporation
Ratings
20
± 12
0.7
2.1
0.3
–55 to +150
415
Tape width
8mm
Units
V
V
A
W
°C
°C/W
Quantity
3000 units
FDG6317NZ Rev B (W)

FDG6317NZ Datasheet
Electrical Characteristics
Symbol
Parameter
TA = 25°C unless otherwise noted
Test Conditions
Min Typ Max Units
Off Characteristics
BVDSS
BVDSS
TJ
IDSS
Drain–Source Breakdown
Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
IGSS Gate–Body Leakage
IGSS Gate–Body Leakage
VGS = 0 V, ID = 250 µA
ID = 250 µA, Referenced to 25°C
VDS = 16 V, VGS = 0 V
VGS = ± 12 V, VDS = 0 V
VGS = ± 4.5 V, VDS = 0 V
On Characteristics (Note 2)
VGS(th)
Gate Threshold Voltage
VGS(th)
TJ
RDS(on)
Gate Threshold Voltage
Temperature Coefficient
Static Drain–Source
On–Resistance
ID(on)
On–State Drain Current
gFS Forward Transconductance
VDS = VGS, ID = 250 µA
ID = –250 µA, Referenced to 25°C
VGS = 4.5 V,
VGS = 2.5 V,
VGS = 4.5 V,
VGS = 4.5 V,
VDS = 5 V,
ID = 0.7 A
ID = 0.6 A
ID = 0.7 A, TJ=125°C
VDS = 5 V
ID = 0.7 A
Dynamic Characteristics
Ciss Input Capacitance
Coss Output Capacitance
Crss Reverse Transfer Capacitance
RG Gate Resistance
VDS = 10 V, V GS = 0 V,
f = 1.0 MHz
VGS = 15 mV, f = 1.0 MHz
Switching Characteristics (Note 2)
td(on) Turn–On Delay Time
tr Turn–On Rise Time
td(off)
Turn–Off Delay Time
tf Turn–Off Fall Time
Qg Total Gate Charge
Qgs Gate–Source Charge
Qgd Gate–Drain Charge
VDD = 10 V, ID = 1 A,
VGS = 4.5 V, RGEN = 6
VDS = 10 V, ID = 0.7 A,
VGS = 4.5 V
Drain–Source Diode Characteristics and Maximum Ratings
IS Maximum Continuous Drain–Source Diode Forward Current
VSD
Drain–Source Diode Forward
VGS = 0 V, IS = 0.25 A (Note 2)
Voltage
trr Diode Reverse Recovery Time IF = 0.7 A, diF/dt = 100 A/µs
Qrr Diode Reverse Recovery Charge
20 V
13 mV/°C
1
± 10
±1
µA
µA
µA
0.6 1.2 1.5
V
–2 mV/°C
300 400
450 550
m
390 560
1A
1.8 S
66.5
19
10
5.8
pF
pF
pF
5.5
7
7.5
2.5
0.76
0.18
0.20
11
15
15
5
1.1
ns
ns
ns
ns
nC
nC
nC
0.25
0.8 1.2
8.3
1.2
A
V
nS
nC
Notes:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
the drain pins. RθJC is guaranteed by design while RθJA is determined by the user's board design. RθJA = 415°C/W when mounted on a minimum pad .
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%
3. The diode connected between the gate and source serves only as protection against ESD. No gate overvoltage rating is implied.
FDG6317NZ Rev B (W)


Features Datasheet pdf FDG6317NZ January 2004 FDG6317NZ Dual 20v N-Channel PowerTrench® MOSFET Gene ral Description This dual N-Channel MOS FET has been designed specifically to i mprove the overall efficiency of DC/DC converters using either synchronous or conventional switching PWM controllers. It has been optimized use in small swi tching regulators, providing an extreme ly low RDS(ON) and gate charge (QG) in a small package. Features • 0.7 A, 2 0 V. RDS(ON) = 400 mΩ @ VGS = 4.5 V R DS(ON) = 550 mΩ @ VGS = 2.5 V • ES D protection diode (note 3) • Low gat e charge • High performance trench te chnology for extremely low RDS(ON) • Compact industry standard SC70-6 surfac e mount package Applications • DC/DC converter • Power management • Loa dswitch S G D D G Pin 1 S SC70-6 Th e pinouts are symmetrical; pin 1 and pi n 4 are interchangeable. Absolute Maxi mum Ratings Symbol VDSS VGSS ID PD TJ, TSTG Drain-Source Voltage Gate-Source V oltage Drain Current – Continuous – Pulsed TA=25oC unless otherwise noted Paramete.
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