Effect Transistor. FDN337N Datasheet

FDN337N Datasheet PDF, Equivalent


Part Number

FDN337N

Description

N-Channel Logic Level Enhancement Mode Field Effect Transistor

Manufacture

Fairchild Semiconductor

Total Page 4 Pages
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FDN337N Datasheet
March 1998
FDN337N
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
SuperSOTTM-3 N-Channel logic level enhancement mode
power field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very
high density process is especially tailored to minimize
on-state resistance. These devices are particularly suited for
low voltage applications in notebook computers, portable
phones, PCMCIA cards, and other battery powered circuits
where fast switching, and low in-line power loss are needed
in a very small outline surface mount package.
Features
2.2 A, 30 V, RDS(ON) = 0.065 @ VGS = 4.5 V
RDS(ON) = 0.082 @ VGS = 2.5 V.
Industry standard outline SOT-23 surface mount
package using proprietary SuperSOTTM-3 design for
superior thermal and electrical capabilities.
High density cell design for extremely low RDS(ON).
Exceptional on-resistance and maximum DC current
capability.
SOT-23
SuperSOTTM-6
SuperSOTTM-8
SO-8
SOT-223
SOIC-16
D
337
SuperSOTTM-3
G
S
Absolute Maximum Ratings TA = 25oC unless other wise noted
Symbol Parameter
VDSS Drain-Source Voltage
VGSS Gate-Source Voltage - Continuous
ID Drain/Output Current - Continuous
- Pulsed
PD Maximum Power Dissipation
(Note 1a)
(Note 1b)
TJ,TSTG Operating and Storage Temperature Range
THERMAL CHARACTERISTICS
RθJA Thermal Resistance, Junction-to-Ambient (Note 1a)
RθJC Thermal Resistance, Junction-to-Case (Note 1)
© 1998 Fairchild Semiconductor Corporation
D
GS
FDN337N
30
±8
2.2
10
0.5
0.46
-55 to 150
250
75
Units
V
V
A
W
°C
°C/W
°C/W
FDN337N Rev.C

FDN337N Datasheet
Electrical Characteristics (TA = 25 OC unless otherwise noted )
Symbol Parameter
Conditions
Min Typ Max Units
OFF CHARACTERISTICS
BVDSS
BVDSS/TJ
IDSS
Drain-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Zero Gate Voltage Drain Current
IGSSF Gate - Body Leakage, Forward
IGSSR Gate - Body Leakage, Reverse
ON CHARACTERISTICS (Note)
VGS = 0 V, ID = 250 µA
ID = 250 µA, Referenced to 25 oC
30
41
V
mV/ oC
VDS = 24 V, VGS = 0 V
1 µA
TJ = 55°C
10 µA
VGS = 8 V,VDS = 0 V
100 nA
VGS = -8 V, VDS = 0 V
-100 nA
VGS(th)
VGS(th)/TJ
RDS(ON)
Gate Threshold Voltage
Gate Threshold Voltage Temp. Coefficient
Static Drain-Source On-Resistance
ID(ON) On-State Drain Current
gFS Forward Transconductance
DYNAMIC CHARACTERISTICS
VDS = VGS, ID = 250 µA
ID = 250 µA, Referenced to 25 oC
VGS = 4.5 V, ID = 2.2 A
TJ =125°C
VGS = 2.5 V, ID = 2 A
VGS = 4.5 V, VDS = 5 V
VDS = 5 V, ID = 2.2 A
0.4 0.7
-2.3
1V
mV/ oC
0.054 0.065
0.08 0.11
0.07 0.082
10 A
13 S
Ciss Input Capacitance
Coss Output Capacitance
Crss Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (Note)
VDS = 10 V, VGS = 0 V,
f = 1.0 MHz
300 pF
145 pF
35 pF
tD(on) Turn - On Delay Time
tr Turn - On Rise Time
VDD = 5 V, ID = 1 A,
VGS = 4.5 V, RGEN = 6
tD(off) Turn - Off Delay Time
tf Turn - Off Fall Time
Qg Total Gate Charge
Qgs Gate-Source Charge
VDS = 10 V, ID = 2.2 A,
VGS = 4.5 V
Qgd Gate-Drain Charge
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
4 10
10 18
17 28
4 10
79
1.1
1.9
ns
ns
ns
ns
nC
nC
nC
IS Maximum Continuous Drain-Source Diode Forward Current
VSD Drain-Source Diode Forward Voltage
VGS = 0 V, IS = 0.42 A (Note)
0.42
0.65 1.2
A
V
Note:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by
design while RθCA is determined by the user's board design.
Typical RθJA using the board layouts shown below on FR-4 PCB in a still air environment :
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
a. 250oC/W when mounted on
0.02 in2 pad of 2oz Cu.
a b. 270oC/W when mounted on
a 0.001 in2 pad of 2oz Cu.
FDN337N Rev.C


Features Datasheet pdf March 1998 FDN337N N-Channel Logic Leve l Enhancement Mode Field Effect Transis tor General Description SuperSOT -3 N-C hannel logic level enhancement mode pow er field effect transistors are produce d using Fairchild's proprietary, high c ell density, DMOS technology. This very high density process is especially tai lored to minimize on-state resistance. These devices are particularly suited f or low voltage applications in notebook computers, portable phones, PCMCIA car ds, and other battery powered circuits where fast switching, and low in-line p ower loss are needed in a very small ou tline surface mount package. TM Featur es 2.2 A, 30 V, RDS(ON) = 0.065 Ω @ V GS = 4.5 V RDS(ON) = 0.082 Ω @ VGS = 2.5 V. Industry standard outline SOT-23 surface mount package using proprietar y SuperSOTTM-3 design for superior ther mal and electrical capabilities. High d ensity cell design for extremely low RD S(ON). Exceptional on-resistance and ma ximum DC current capability. SOT-23 SuperSOTTM-6 SuperSOTTM-8 S.
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