FDN358P

March 1998 FDN358P P-Channel Logic Level Enhancement Mode Field Effect Transistor General Description SuperSOTTM-3 P-Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications in notebook computers, portable phones, PCMCIA cards, and other battery powered circuits where fast switching, and low in-line power loss are needed in a very small outline surface mount package. Features -1.5 A, -30 V, RDS(ON) = 0.125 Ω @ VGS = -10 V RDS(ON) = 0.20 Ω @ VGS = - 4.5 V. High power version of industry SOT-23 package: identical pin out to SOT-23; 30% higher power handling capability. High density cell design for extremely low RDS(ON). Exceptional on-resistance and maximum DC current capability. SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SO-8 SOT-223 SOIC-16 D D 8 35 S G S SuperSOT -3 TM G Absolute Maximum Ratings Symbol VDSS VGSS ID PD TJ,TSTG RθJA RθJC Parameter Drain-Source Voltage Gate-Source Voltage TA = 25oC unless other wise noted FDN358P -30 ±20 -1.5 -5 (Note 1a) (Note 1b) Units V V A Drain/Output Current - Continuous - Pulsed Maximum Power Dissipation 0.5 0.46 -55 to 150 W Operating and Storage Temperature Range °C THERMAL CHARACTERISTICS Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Case (Note 1a) (...