Effect Transistor. FDR856P Datasheet

FDR856P Datasheet PDF, Equivalent


Part Number

FDR856P

Description

P-Channel Logic Level Enhancement Mode Field Effect Transistor

Manufacture

Fairchild Semiconductor

Total Page 8 Pages
PDF Download
Download FDR856P Datasheet


FDR856P Datasheet
March 1998
FDR856P
P-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
SuperSOTTM-8 P-Channel enhancement mode power field
effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very
high density process is especially tailored to minimize
on-state resistance and provide superior switching
performance. These devices are particularly suited for low
voltage applications such as battery powered circuits or
portable electronics where low in-line power loss, fast
switching and resistance to transients are needed.
Features
- 6.3 A, -30 V, RDS(ON) =0.025 @ VGS = -10 V
RDS(ON) =0.040 @ VGS = -4.5 V.
SuperSOTTM-8 package:
small footprint (40% less than SO-8);low profile (1mm
thick);maximum power comperable to SO-8.
High density cell design for extremely low RDS(ON).
SOT-23
SuperSOTTM-6
SuperSOTTM-8
SO-8
SOT-223
SOIC-16
S
D
D
S
856P
G
D
Dpin 1
SuperSOT TM-8
D
Absolute Maximum Ratings TA = 25oC unless other wise noted
Symbol Parameter
VDSS Drain-Source Voltage
VGSS Gate-Source Voltage - Continuous
ID Maximum Drain Current - Continuous (Note 1a)
- Pulsed
PD Maximum Power Dissipation
(Note 1a)
(Note 1b)
(Note 1c)
TJ,TSTG Operating and Storage Temperature Range
THERMAL CHARACTERISTICS
RθJA Thermal Resistance, Junction-to-Ambient (Note 1a)
RθJC Thermal Resistance, Junction-to-Case (Note 1)
© 1998 Fairchild Semiconductor Corporation
54
63
72
81
FDR856P
-30
±20
-5.1
-50
1.8
1
0.9
-55 to 150
50
25
Units
V
V
A
W
°C
°C/W
°C/W
FDR856P Rev.B

FDR856P Datasheet
Electrical Characteristics (TA = 25 OC unless otherwise noted )
Symbol Parameter
Conditions
Min Typ Max Units
OFF CHARACTERISTICS
BVDSS
BVDSS/TJ
IDSS
Drain-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Zero Gate Voltage Drain Current
IGSSF Gate - Body Leakage, Forward
IGSSR Gate - Body Leakage, Reverse
ON CHARACTERISTICS (Note 2)
VGS = 0 V, I D = -250 µA
ID = -250 µA, Referenced to 25 oC
-30
-15
V
mV /oC
VDS = -24 V, VGS = 0 V
-1 µA
TJ = 55°C
-10 µA
VGS = -20 V, VDS = 0 V
-100 nA
VGS = -20 V, VDS = 0 V
-100 nA
VGS(th)
VGS(th)/TJ
RDS(ON)
Gate Threshold Voltage
Gate Threshold Voltage Temp. Coefficient
Static Drain-Source On-Resistance
ID(ON) On-State Drain Current
gFS Forward Transconductance
DYNAMIC CHARACTERISTICS
VDS = VGS, ID = -250 µA
ID = -250 µA, Referenced to 25 oC
-1 -1.5
3
-3 V
mV /oC
VGS = -10 V, I D = -6.3 A
0.022 0.025
TJ =125°C
0.03 0.042
VGS = -4.5 V, I D = -5 A
0.033 0.04
VGS = -10 V, VDS = -5 V
-50
A
VDS = -10 V, I D = -6.3 A
15 S
Ciss Input Capacitance
Coss Output Capacitance
Crss Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (Note 2)
VDS = -15 V, VGS = 0 V,
f = 1.0 MHz
1370
740
220
pF
pF
pF
tD(on) Turn - On Delay Time
VDS = -15 V, I D= -1 A
tr Turn - On Rise Time
VGS = -10 V , RG = 6
tD(off) Turn - Off Delay Time
tf Turn - Off Fall Time
Qg Total Gate Charge
VDS = -15 V, I D = -6.3 A,
Qgs Gate-Source Charge
VGS = -10 V
Qgd Gate-Drain Charge
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
7 14
12 19
80 100
130 160
22 31
3.8
8.7
ns
ns
ns
ns
nC
nC
nC
IS Maximum Continuous Drain-Source Diode Forward Current
VSD Drain-Source Diode Forward Voltage
VGS = 0 V, IS = -1.3 A (Note 2)
-0.73
-1.3
-1.2
A
V
Notes:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by
design while RθCA is determined by the user's board design.
a. 50OC/W on a 0.5 in2
pad of 2oz copper.
b. 105OC/W on a 0.02 in2
pad of 2oz copper.
c. 125OC/W on a 0.003 in2 pad
of 2oz copper.
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
FDR856P Rev.B


Features Datasheet pdf March 1998 FDR856P P-Channel Logic Leve l Enhancement Mode Field Effect Transis tor General Description SuperSOTTM-8 P- Channel enhancement mode power field ef fect transistors are produced using Fai rchild's proprietary, high cell density , DMOS technology. This very high densi ty process is especially tailored to mi nimize on-state resistance and provide superior switching performance. These d evices are particularly suited for low voltage applications such as battery po wered circuits or portable electronics where low in-line power loss, fast swit ching and resistance to transients are needed. Features - 6.3 A, -30 V, RDS(O N) =0.025 Ω @ VGS = -10 V RDS(ON) =0. 040 Ω @ VGS = -4.5 V. SuperSOTTM-8 pa ckage: small footprint (40% less than S O-8);low profile (1mm thick);maximum po wer comperable to SO-8. High density ce ll design for extremely low RDS(ON). S OT-23 SuperSOTTM-6 SuperSOTTM-8 SO-8 SOT-223 SOIC-16 D D S S 6 85 P G 5 6 4 3 2 1 pin 1 SuperSOT TM-8 D D D 7 8 Absolute Maximu.
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