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FAN8400D (FAN8400BD3)
3-Phase BLDC Motor Driver with PLL
Features
• • • • • • • 3-Phase BLDC motor driver IC with speed control Phase Locked Loop (PLL) speed control Built-in phase locked detector output Current linear drive scheme External clock for arbitrary motor speed Built-in FG amplifier and integrating amplifier Auto Gain Control (AGC) circuit for compensation hall amplifier • Built-in protection circuits (over-current limit, under voltage limit, thermal shut down)
Description
The FAN8400D is a monolithic integrated circuit. it is one driver for laser beam printer (LBP) polygon mirror motor, which has single chip implementation of all circuits. For extremely high rotational precision, it employs the phase locked loop (PLL) speed control scheme.
28-SSOPH-375SG2
Typical application
• • • • • Polygon mirror motor drive IC for laser beam printer Polygon mirror motor drive IC for facsimile Polygon mirror motor drive IC for duplicator Polygon mirror motor drive IC for multi function printer General 3 phase BLDC motor drive IC
Ordering Information
Device
FAN8400BD3
Package
28-SSOPH-375SG2
Operating Temp
−20°C ~ +80°C −20°C ~ +80°C
FAN8400BD3TF 28-SSOPH-375SG2
Rev.1.0.1
©2001 Fairchild Semiconductor Corporation
FAN8400D (FAN8400BD3)
Pin Assignments
AGC FGINFGS FGOUT S/S NC NC
1 2 3 4 5 6 7
28 27 26 25 24 23 22
HWHW+ HUHU+ HVHV+ W
FIN
FAN8400D
FIN
SGND LD ECLK PD EI EO FC
8 9 10 11 12 13 14
21 20 19 18 17 16 15
V U RF PGND VCC VREG NC
2
FAN8400D (FAN8400BD3)
Pin Definitions
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Pin Name AGC FGINFGS FGOUT S/S NC NC SGND LD ECLK PD EI EO FC NC VREG VCC PGND RF U V W HV+ HVHU+ HUHW+ HWSignal ground Phase locked loop detector output External clock Phase locked loop detector output Error amplifier inverting input Error amplifier output Control amplifier frequency correction Regulator voltage stabilization output Power supply Power ground Output current detection U output V output W output V hall amplifier non inverting input V hall amplifier inverting input U hall amplifier non inverting input U hall amplifier inverting input W hall amplifier non inverting input W hall amplifier inverting input Pin Function Description AGC amplifier frequency characteristics correction FG amplifier inverting input FG pulse output FG amplifier output Stop and start -
3
FAN8400D (FAN8400BD3)
Internal Block Diagram
AGC FGINFGS FGOUT S/S NC NC
1 2 3 4 5 6 7
AGC
28 27
HWHW+ HUHU+ HVHV+ W
+
+
VREG 2
Hall AMP Matrix
26 25 24 23 22
S/S
PLL FIN Clock Output Controller FIN
SGND LD ECLK PD EI EO FC
8 9 10 11 12 13 14 Lock Detector V-type Control OCL TSD & UVLO
21 20 19 18 17 Regulator 16 15
V U RF PGND VCC VREG NC
+
VREG 2
4
FAN8400D (FAN8400BD3)
Absolute Maximum Ratings (Ta = 25°C)
Parameter Maximum supply voltage Maximum output current Power dissipation Operating temperature Storage temperature Symbol VCCMAX IOMAX Pd TOPR TSTG Value 30 0.6 1.7 −20 ~ +80 −50 ~ +150 Unit V A W °C °C Remark -
Recommended Operating Conditions (Ta = 25°C)
Parameter Operating voltage range Symbol VCC Min. 20 Typ. 24 Max. 28 Unit V
5
FAN8400D (FAN8400BD3)
Electrical Characteristics (Ta = 25°C)
Parameter POWER SUPPLY CURRENT Low power supply current Typical power supply current High power supply current U source saturation voltage (1) U source saturation voltage (2) U sink saturation voltage (1) U sink saturation voltage (2) V source saturation voltage (1) V source saturation voltage (2) V sink saturation voltage (1) V sink saturation voltage (2) W source saturation voltage (1) W source saturation voltage (2) W sink saturation voltage (1) W sink saturation voltage (2) U output leakage current V output leakage current W output leakage current UNDER VOLTAGE LIMIT UVLO operating voltage UVLO hysteresis REGULATOR VOLTAGE OUTPUT Regulator output voltage Power supply variation Load variation HALL AMPLIFIER INPUT BLOCK HU+ hall AMP input bias current HU− hall AMP input bias current HV+ hall AMP input bias current HV− hall AMP input bias current HW+ hall AMP input bias current HW− hall AMP input bias current Hall differential input range Hall common input range IBHA1+ IBHA1− IBHA2+ IBHA2− IBHA3+ IBHA3− VHIN VICM Sine wave input Differential input : 50mVp-p 50 3.5 2 2 2 2 2 2 10 10 10 10 10 10 350 VCC-3.5 µA µA µA µA µA µA mVp-p V VREG HVREG1 HVREG2 VCC=20~28V ILOAD=0~10mA 5.8 6.3 6.8 100 100 V mV mV VSD HVSD 7.0 1.0 7.6 1.3 8.2 1.6 V V ICCL ICCT ICCH VSATUU1 VSATUU2 VSATUL1 VSATUL2 VSATVU1 VSATVU2 VSATVL1 VSATVL2 VSATWU1 VSATWU2 VSATWL1 VSATWL2 IOLEAKU IOLEAKV IOLEAKW Stop mode, VCC=20V Stop mode, VCC=24V Stop mode, VCC=28V IO=0.6A, RF=0Ω IO=0.3A, RF=0Ω IO=0.6A, RF=0Ω IO=0.3A, RF=0Ω IO=0.6A, RF=0Ω IO=0.3A, RF=0Ω IO=0.6A, RF=0Ω IO=0.3A, RF=0Ω IO=0.6A, RF=0Ω IO=0.3A, RF=0Ω IO=0.6A, RF=0Ω IO=0.3A, RF=0Ω VCC=28V, U=28V VCC=28V, V=28V VCC=28V, W=28V 20 21 22 30 31 32 1.8 1.6 0.5 0.25 1.8 1.6 0.5 0.25 1.8 1.6 0.5 0.25 40 41.