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EPM7128AE Dataheets PDF



Part Number EPM7128AE
Manufacturers Altera Corporation
Logo Altera Corporation
Description Programmable Logic Device
Datasheet EPM7128AE DatasheetEPM7128AE Datasheet (PDF)

MAX 7000A ® Includes MAX 7000AE Programmable Logic Device Data Sheet October 2002, ver. 4.3 Features... ■ ■ ■ ■ ■ ■ ■ ■ High-performance 3.3-V EEPROM-based programmable logic devices (PLDs) built on second-generation Multiple Array MatriX (MAX®) architecture (see Table 1) 3.3-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability – MAX 7000AE device in-system programmability (ISP) circuitry co.

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MAX 7000A ® Includes MAX 7000AE Programmable Logic Device Data Sheet October 2002, ver. 4.3 Features... ■ ■ ■ ■ ■ ■ ■ ■ High-performance 3.3-V EEPROM-based programmable logic devices (PLDs) built on second-generation Multiple Array MatriX (MAX®) architecture (see Table 1) 3.3-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability – MAX 7000AE device in-system programmability (ISP) circuitry compliant with IEEE Std. 1532 – EPM7128A and EPM7256A device ISP circuitry compatible with IEEE Std. 1532 Built-in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1 Supports JEDEC Jam Standard Test and Programming Language (STAPL) JESD-71 Enhanced ISP features – Enhanced ISP algorithm for faster programming (excluding EPM7128A and EPM7256A devices) – ISP_Done bit to ensure complete programming (excluding EPM7128A and EPM7256A devices) – Pull-up resistor on I/O pins during in-system programming Pin-compatible with the popular 5.0-V MAX 7000S devices High-density PLDs ranging from 600 to 10,000 usable gates Extended temperature range f For information on in-system programmable 5.0-V MAX 7000 or 2.5-V MAX 7000B devices, see the MAX 7000 Programmable Logic Device Family Data Sheet or the MAX 7000B Programmable Logic Device Family Data Sheet. Altera Corporation DS-M7000A-4.3 1 MAX 7000A Programmable Logic Device Data Sheet Table 1. MAX 7000A Device Features Feature Usable gates Macrocells Logic array blocks Maximum user I/O pins tPD (ns) tSU (ns) tFSU (ns) tCO1 (ns) fCNT (MHz) EPM7032AE 600 32 2 36 4.5 2.9 2.5 3.0 227.3 ■ ■ ■ EPM7064AE 1,250 64 4 68 4.5 2.8 2.5 3.1 222.2 EPM7128AE 2,500 128 8 100 5.0 3.3 2.5 3.4 192.3 EPM7256AE 5,000 256 16 164 5.5 3.9 2.5 3.5 172.4 EPM7512AE 10,000 512 32 212 7.5 5.6 3.0 4.7 116.3 ...and More Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 4.5-ns pin-to-pin logic delays with counter frequencies of up to 227.3 MHz MultiVoltTM I/O interface enables device core to run at 3.3 V, while I/O pins are compatible with 5.0-V, 3.3-V, and 2.5-V logic levels Pin counts ranging from 44 to 256 in a variety of thin quad flat pack (TQFP), plastic quad flat pack (PQFP), ball-grid array (BGA), spacesaving FineLine BGATM , and plastic J-lead chip carrier (PLCC) packages Supports hot-socketing in MAX 7000AE devices Programmable interconnect array (PIA) continuous routing structure for fast, predictable performance PCI-compatible Bus-friendly architecture, including programmable slew-rate control Open-drain output option Programmable macrocell registers with individual clear, preset, clock, and clock enable controls Programmable power-up states for macrocell registers in MAX 7000AE devices Programmable power-saving mode for 50% or greater power reduction in each macrocell Configurable expander product-term distribution, allowing up to 32 product terms per macrocell Programmable security bit for protection of proprietary designs 6 to 10 pin- or logic-driven output enable signals Two global clock signals with optional inversion Enhanced interconnect resources for improved routability Fast input setup times provided by a dedicated path from I/O pin to macrocell registers Programmable output slew-rate control Programmable ground pins 2 Altera Corporation MAX 7000A Programmable Logic Device Data Sheet ■ ■ ■ Software design support and automatic place-and-route provided by Altera’s development systems for Windows-based PCs and Sun SPARCstation, and HP 9000 Series 700/800 workstations Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, and VeriBest Programming support with Altera’s Master Programming Unit (MPU), MasterBlasterTM serial/universal serial bus (USB) communications cable, ByteBlasterMVTM parallel port download cable, and BitBlasterTM serial download cable, as well as programming hardware from third-party manufacturers and any JamTM STAPL File (.jam), Jam Byte-Code File (.jbc), or Serial Vector Format File- (.svf) capable in-circuit tester General Description MAX 7000A (including MAX 7000AE) devices are high-density, highperformance devices based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROMbased MAX 7000A devices operate with a 3.3-V supply voltage and provide 600 to 10,000 usable gates, ISP, pin-to-pin delays as fast as 4.5 ns, and counter speeds of up to 227.3 MHz. MAX 7000A devices in the -4, -5, -6, -7, and some -10 speed grades are compatible with the timing requirements for 33 MHz operation of the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2. See Table 2. Table 2. MAX 7000A Speed Grades Device -4 EPM7032AE EPM7064AE EPM7128A EPM7128AE EPM7256A E.


EPM7064AE EPM7128AE EPM7256AE


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