DS26S10

DS26S10 Quad Bus Transceiver May 1999 DS26S10 Quad Bus Transceiver General Description The DS26S10 is a quad Bus Transceiver consisting of 4 high speed bus drivers with open-collector outputs capable of sinking 100 mA at 0.8V and 4 high speed bus receivers. Each driver output is connected internally to the high speed bus receiver in addition to being connected to the package pin. The receiver has a Schottky TTL output capable of driving 10 Schottky TTL unit loads. An active low enable gate controls the 4 drivers so that outputs of different device drivers can be connected together for party-line operation. The bus output high-drive capability in the low state allows party-line operation with a line impedance as low as 100Ω. The line can be terminated at both ends, and still give considerable noise margin at the receiver. The receiver typical switching point is 2V. The DS26S10 features advanced Schottky processing to minimize propagation delay. The device package also has 2 ground pins to improve ground current handling and allow close decoupling between VCC and ground at the package. Both GND 1 and GND 2 should be tied to the ground bus external to the device package. Features n n n n n Input to bus is inverting on DS26S10 Quad high speed open-collector bus transceivers Driver outputs can sink 100 mA at 0.8V maximum Advanced Schottky processing PNP inputs to reduce input loading Logic Diagrams DS2610 DS005802-1 © 1999 National Semiconductor Corporation DS005802 www.na...