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DS36C280

National Semiconductor

Slew Rate Controlled CMOS EIA-RS-485 Transceiver

DS36C280 Slew Rate Controlled CMOS EIA-RS-485 Transceiver July 1998 DS36C280 Slew Rate Controlled CMOS EIA-RS-485 Tran...


National Semiconductor

DS36C280

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Description
DS36C280 Slew Rate Controlled CMOS EIA-RS-485 Transceiver July 1998 DS36C280 Slew Rate Controlled CMOS EIA-RS-485 Transceiver General Description The DS36C280 is a low power differential bus/line transceiver designed to meet the requirements of RS-485 Standard for multipoint data transmission. In addition, it is compatible with TIA/EIA-422-B. The slew rate control feature allows the user to set the driver rise and fall times by using an external resistor. Controlled edge rates can reduce switching EMI. The CMOS design offers significant power savings over its bipolar and ALS counterparts without sacrificing ruggedness against ESD damage. The device is ideal for use in battery powered or power conscious applications. ICC is specified at 500 µA maximum. The driver and receiver outputs feature TRI-STATE ® capability. The driver outputs operate over the entire common mode range of −7V to +12V. Bus contention or fault situations are handled by a thermal shutdown circuit, which forces the driver outputs into the high impedance state. The receiver incorporates a fail safe circuit which guarantees a high output state when the inputs are left open (Note 1) . Features n 100% RS-485 compliant — Guaranteed RS-485 device interoperation n Low power CMOS design: ICC 500 µA max n Adjustable slew rate control — Minimizes EMI affects n Built-in power up/down glitch-free circuitry — Permits live transceiver insertion/displacement n DIP and SOIC packages available n Industrial temperature ran...




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