LVDS Transmitter. DS90C363A Datasheet

DS90C363A Transmitter. Datasheet pdf. Equivalent

DS90C363A Datasheet
Recommendation DS90C363A Datasheet
Part DS90C363A
Description +3.3V Programmable LVDS Transmitter
Feature DS90C363A; DS90C363A/DS90CF363A +3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link-65 MHz.
Manufacture National Semiconductor
Datasheet
Download DS90C363A Datasheet




National Semiconductor DS90C363A
June 1998
DS90C363A/DS90CF363A
+3.3V Programmable LVDS Transmitter 18-Bit Flat Panel
Display (FPD) Link-65 MHz
+3.3V LVDS Transmitter 18-Bit Flat Panel Display (FPD)
Link-65 MHz
General Description
The DS90C363A/DS90CF363A transmitter converts 21 bits
of CMOS/TTL data into three LVDS (Low Voltage Differential
Signaling) data streams. A phase-locked transmit clock is
transmitted in parallel with the data streams over a fourth
LVDS link. Every cycle of the transmit clock 21 bits of input
data are sampled and transmitted. At a transmit clock fre-
quency of 65 MHz, 18 bits of RGB data and 3 bits of LCD
timing and control data (FPLINE, FPFRAME, DRDY) are
transmitted at a rate of 455 Mbps per LVDS data channel.
Using a 65 MHz clock, the data throughput is 170 Mbytes/
sec. The DS90C363A transmitter can be programmed for
Rising edge strobe or Falling edge strobe through a dedi-
cated pin. The DS90CF363A is fixed as a Falling edge
strobe transmitter. A Rising edge or Falling edge strobe
transmitter will interoperate with a Falling edge strobe Re-
ceiver (DS90CF364) without any translation logic.
This chipset is an ideal means to solve EMI and cable size
problems associated with wide, high speed TTL interfaces.
Features
n 20 to 65 MHz shift clock support
n Rejects > ± 3ns Jitter from VGA chip with less than
225ps output Jitter @65MHz (TJCC)
n Best–in–Class Set & Hold Times on TxINPUTs
n Tx power consumption <130 mW (typ) @65MHz
Grayscale
n >50% Less Power Dissipation than BiCMOS
Alternatives
n Tx Power-down mode <200µW (max)
n ESD rating >7 kV (HBM), >500V (EIAJ)
n Supports VGA, SVGA, XGA and Dual Pixel SXGA.
n Narrow bus reduces cable size and cost
n Up to 1.3 Gbps throughput
n Up to 170 Megabytes/sec bandwidth
n 345 mV (typ) swing LVDS devices for low EMI
n PLL requires no external components
n Compatible with TIA/EIA-644 LVDS standard
n Low profile 48-lead TSSOP package
n Improved replacement for:
SN75LVDS85 — DS90C363A
SN75LVDS84 — DS90CF363A
Block Diagrams
DS90C363A/DS90CF363A
DS100138-1
Order Number DS90C363AMTD or DS90CF363AMTD
See NS Package Number MTD48
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1998 National Semiconductor Corporation DS100138
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National Semiconductor DS90C363A
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VCC)
CMOS/TTL Input Voltage
LVDS Driver Output Voltage
LVDS Output Short Circuit
Duration
−0.3V to +4V
−0.3V to (VCC + 0.3V)
−0.3V to (VCC + 0.3V)
Continuous
Junction Temperature
+150˚C
Storage Temperature
−65˚C to +150˚C
Lead Temperature
(Soldering, 4 sec)
+260˚C
Maximum Package Power Dissipation Capacity @ 25˚C
MTD48 (TSSOP) Package:
DS90C363A/DS90CF363A
1.98 W
Package Derating:
DS90C363A/DS90CF363A
16 mW/˚C above +25˚C
ESD Rating
(HBM, 1.5 k, 100 pF)
(EIAJ, 0, 200 pF)
> 7 kV
> 500V
Recommended Operating
Conditions
Supply Voltage (VCC)
Operating Free Air
Temperature (TA)
Receiver Input Range
Supply Noise Voltage (VCC)
TxCLKIN frequency
Min Nom Max
3.0 3.3 3.6
Units
V
−10 +25 +70
˚C
0 2.4 V
100 mVPP
18 68 MHz
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
CMOS/TTL DC SPECIFICATIONS
VIH High Level Input Voltage
VIL Low Level Input Voltage
VCL Input Clamp Voltage
IIN Input Current
LVDS DC SPECIFICATIONS
VOD
VOD
Differential Output Voltage
Change in VOD between
complimentary output states
VOS
VOS
Offset Voltage (Note 4)
Change in VOS between
complimentary output states
IOS Output Short Circuit Current
IOZ Output TRI-STATE® Current
TRANSMITTER SUPPLY CURRENT
ICCTW Transmitter Supply Current
Worst Case
ICCTG Transmitter Supply Current
16 Grayscale
ICCTZ
Transmitter Supply Current
Power Down
Conditions
Min Typ Max Units
ICL = −18 mA
V IN = 0.4V, 2.5V or VCC
V IN = GND
RL = 100
VOUT = 0V, RL = 100
Power Down = 0V,
VOUT = 0V or VCC
RL = 100,
CL = 5 pF,
Worst Case Pattern
(Figures 1, 4)
f = 32.5 MHz
f = 37.5 MHz
f = 65 MHz
RL = 100,
CL = 5 pF,
16 Grayscale Pattern
(Figures 2, 4)
f = 32.5 MHz
f = 37.5 MHz
f = 65 MHz
Power Down = Low
Driver Outputs in TRI-STATE® under
Power Down Mode
2.0
GND
−10
−0.79
+1.8
0
VCC
0.8
−1.5
+10
250 345 450
35
1.125 1.25 1.375
35
−3.5 −5
±1 ±10
31 43
33 45
39 52
23 35
28 40
33 45
10 55
V
V
V
µA
µA
mV
mV
V
mV
mA
µA
mA
mA
mA
mA
mA
mA
µA
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2: Typical values are given for VCC = 3.3V and T A = +25C.
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise speci-
fied (except VOD and VOD ).
Note 4: VOS previously referred as VCM.
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National Semiconductor DS90C363A
Recommended Transmitter Input Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
TCIT
TxCLK IN Transition Time (Figure 5 )
TCIP
TxCLK IN Period (Figure 6 )
TCIH
TxCLK IN High Time (Figure 6 )
TCIL
TxCLK IN Low Time (Figure 6 )
Min
14.7
0.35T
0.35T
Typ
T
0.5T
0.5T
Max
5
55.6
0.65T
0.65T
Units
ns
ns
ns
ns
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
LLHT
LHLT
TPPos0
TPPos1
TPPos2
TPPos3
TPPos4
TPPos5
TPPos6
TPPos0
TPPos1
TPPos2
TPPos3
TPPos4
TPPos5
TPPos6
TPPos0
TPPos1
TPPos2
TPPos3
TPPos4
TPPos5
TPPos6
TSTC
THTC
TCCD
TJCC
Parameter
LVDS Low-to-High Transition Time (Figure 4 )
LVDS High-to-Low Transition Time (Figure 4 )
Transmitter Output Pulse Position for Bit 0 (Figure 11 ) (Note 5)
Transmitter Output Pulse Position for Bit 1
Transmitter Output Pulse Position for Bit 2
Transmitter Output Pulse Position for Bit 3
Transmitter Output Pulse Position for Bit 4
Transmitter Output Pulse Position for Bit 5
Transmitter Output Pulse Position for Bit 6
Transmitter Output Pulse Position for Bit 0 (Figure 11 ) (Note 5)
Transmitter Output Pulse Position for Bit 1
Transmitter Output Pulse Position for Bit 2
Transmitter Output Pulse Position for Bit 3
Transmitter Output Pulse Position for Bit 4
Transmitter Output Pulse Position for Bit 5
Transmitter Output Pulse Position for Bit 6
Transmitter Output Pulse Position for Bit 0 (Figure 11 ) (Note 5)
Transmitter Output Pulse Position for Bit 1
Transmitter Output Pulse Position for Bit 2
Transmitter Output Pulse Position for Bit 3
Transmitter Output Pulse Position for Bit 4
Transmitter Output Pulse Position for Bit 5
Transmitter Output Pulse Position for Bit 6
TxIN Setup to TxCLK IN (Figure 6 )
TxIN Hold to TxCLK IN (Figure 6 )
TxCLK IN to TxCLK OUT Delay (Figure 7 ) T A=25˚C, VCC=3.3V
TxCLK IN to TxCLK OUT Delay (Figure 7 )
Transmitter Jitter Cycle-to-Cycle (Figures 12, 13 ) (Note 6)
TPLLS
TPDD
Transmitter Phase Lock Loop Set (Figure 8 )
Transmitter Power Down Delay (Figure 10 )
f = 65 MHz
f = 40 MHz
f = 32.5
MHz
f = 65 MHz
f = 40 MHz
f = 32.5
MHz
Min
−0.30
1.90
4.10
6.30
8.50
10.70
12.90
−0.35
3.22
6.79
10.36
13.93
17.51
21.08
−0.40
4.00
8.40
12.80
17.20
21.60
26.00
2.5
0
3
3
Typ
0.75
0.75
0
2.20
4.40
6.60
8.80
11.00
13.20
0
3.57
7.14
10.71
14.28
17.86
21.43
0
4.40
8.80
13.20
17.60
22.00
26.40
175
240
260
Max
1.5
1.5
0.20
2.40
4.60
6.80
9.00
11.20
13.40
0.35
3.92
7.49
11.06
14.63
18.21
21.78
0.40
4.80
9.20
13.60
18.00
22.40
26.80
5.5
7.0
225
380
400
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
ps
10 ms
100 ns
Note 5: The Minimum and Maximum Limits are based on statistical analysis of the device performance over process, voltage, and temperature ranges. This param-
eter is functionality tested only on Automatic Test Equipment (ATE).
Note 6: The Limits are based on statistical analysis of the device performance over process, voltage, and temperature ranges. Output jitter is measured with a cycle-
to-cycle jitter of 3ns applied to the input clock signal. A jitter event of 3ns, represents worse case jump in the clock edge from most Graphics controller VGA chips
currently available. This parameter is used when calculating system margin (RSKM). See Figures 12, 13 and AN-1059.
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