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DS92LV090A Dataheets PDF



Part Number DS92LV090A
Manufacturers National Semiconductor
Logo National Semiconductor
Description 9 Channel Bus LVDS Transceiver
Datasheet DS92LV090A DatasheetDS92LV090A Datasheet (PDF)

DS92LV090A9 Channel Bus LVDS Transceiver April 2000 DS92LV090A 9 Channel Bus LVDS Transceiver General Description The DS92LV090A is one in a series of Bus LVDS transceivers designed specifically for the high speed, low power proprietary backplane or cable interfaces. The device operates from a single 3.3V power supply and includes nine differential line drivers and nine receivers. To minimize bus loading, the driver outputs and receiver inputs are internally connected. The separate I/O of the .

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DS92LV090A9 Channel Bus LVDS Transceiver April 2000 DS92LV090A 9 Channel Bus LVDS Transceiver General Description The DS92LV090A is one in a series of Bus LVDS transceivers designed specifically for the high speed, low power proprietary backplane or cable interfaces. The device operates from a single 3.3V power supply and includes nine differential line drivers and nine receivers. To minimize bus loading, the driver outputs and receiver inputs are internally connected. The separate I/O of the logic side allows for loop back support. The device also features a flow through pin out which allows easy PCB routing for short stubs between its pins and the connector. The driver translates 3V TTL levels (single-ended) to differential Bus LVDS (BLVDS) output levels. This allows for high speed operation, while consuming minimal power with reduced EMI. In addition, the differential signaling provides common mode noise rejection of ± 1V. The receiver threshold is less than ± 100 mV over a ± 1V common mode range and translates the differential Bus LVDS to standard (TTL/CMOS) levels. (See Applications Information Section for more details.) Features n n n n n n n n n n n n n n n n Bus LVDS Signaling 3.2 nanosecond propagation delay max Chip to Chip skew ± 800ps Low power CMOS design High Signaling Rate Capability (above 100 Mbps) 0.1V to 2.3V Common Mode Range for VID = 200mV ± 100 mV Receiver Sensitivity Supports open and terminated failsafe on port pins 3.3V operation Glitch free power up/down (Driver & Receiver disabled) Light Bus Loading (5 pF typical) per Bus LVDS load Designed for Double Termination Applications Balanced Output Impedance Product offered in 64 pin TQFP package High impedance Bus pins on power off (VCC = 0V) Driver Channel to Channel skew (same device) 230ps typical n Receiver Channel to Channel skew (same device) 370ps typical Simplified Functional Diagram DS100111-1 TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 2000 National Semiconductor Corporation DS100111 www.national.com DS92LV090A Connection Diagram DS100111-2 Top View Order Number DS92LV090ATVEH See NS Package Number VEH064DB Pinout Description Pin Name DO+/RI+ DO−/RI− DIN RO RE DE GND VCC AGND AVCC NC Pin # 27, 31, 35, 37, 41, 45, 47, 51, 55 26, 30, 34, 36, 40, 44, 46, 50, 54 2, 6, 12, 18, 20, 22, 58, 60, 62 3, 7, 13, 19, 21, 23, 59, 61, 63 17 16 4, 5, 9, 14, 25, 56 10, 15, 24, 57, 64 28, 33, 43, 49, 53 29, 32, 42, 48, 52 1, 8, 11, 38, 39 Input/Output I/O I/O I O I I Power Power Power Power N/A Descriptions True Bus LVDS Driver Outputs and Receiver Inputs. Complimentary Bus LVDS Driver Outputs and Receiver Inputs. TTL Driver Input. TTL Receiver Output. Receiver Enable TTL Input (Active Low). Driver Enable TTL Input (Active High). Ground for digital circuitry (must connect to GND on PC board). These pins connected internally. VCC for digital circuitry (must connect to VCC on PC board). These pins connected internally. Ground for analog.


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