AV16841DL

INTEGRATED CIRCUITS 74ALVT16841 2.5V/3.3V ALVT 20-bit bus interface latch (3-State) Product specification Supersedes data of 1996 Aug 28 IC23 Data Handbook 1998 Feb 13 Philips Semiconductors Philips Semiconductors Product specification 2.5V/3.3V 20-bit bus interface latch (3-State) 74ALVT16841 FEATURES High speed parallel latches 5V I/O Compatible Live insertion/extraction permitted Extra data width for wide address/data paths or buses carrying Power-up 3-State Power-up reset Ideal where high speed, light loading, or increased fan-in are required with MOS microprocessors parity DESCRIPTION The 74ALVT16841 Bus interface latch is designed to provide extra data width for wider data/address paths of buses carrying parity. It is designed for VCC operation at 2.5V or 3.3V with I/O compatibility to 5V. The 74ALVT16841 consists of two sets of ten D-type latches with 3-State outputs. The flip-flops appear transparent to the data when Latch Enable (nLE) is High. This allows asynchronous operation, as the output transition follows the data in transition. On the nLE High-to-Low transition, the data that meets the setup and hold time is latched. Data appears on the bus when the Output Enable (nOE) is Low. When nOE is High the output is in the High-impedance state. Output capability: +64mA/–32mA Latch-up protection exceeds 500mA per Jedec Std 17 Bus-hold data inputs eliminate the need for external pull-up ESD protection exceeds 2000V per MIL STD 883 Method 3...