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M27V405 Dataheets PDF



Part Number M27V405
Manufacturers STMicroelectronics
Logo STMicroelectronics
Description 4 Mbit 512Kb x 8 Low Voltage OTP EPROM
Datasheet M27V405 DatasheetM27V405 Datasheet (PDF)

M27V512 512 Kbit (64Kb x8) Low Voltage UV EPROM and OTP EPROM s LOW VOLTAGE READ OPERATION: 3V to 3.6V FAST ACCESS TIME: 100ns LOW POWER CONSUMPTION: – Active Current 10mA at 5MHz – Standby Current 10µA 28 28 s s s s s PROGRAMMING VOLTAGE: 12.75V ± 0.25V PROGRAMMING TIME: 100µs/byte (typical) ELECTRONIC SIGNATURE – Manufacturer Code: 20h – Device Code: 3Dh 1 1 FDIP28W (F) PDIP28 (B) DESCRIPTION The M27V512 is a low voltage 512 Kbit EPROM offered in the two ranges UV (ultra viloet erase).

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M27V512 512 Kbit (64Kb x8) Low Voltage UV EPROM and OTP EPROM s LOW VOLTAGE READ OPERATION: 3V to 3.6V FAST ACCESS TIME: 100ns LOW POWER CONSUMPTION: – Active Current 10mA at 5MHz – Standby Current 10µA 28 28 s s s s s PROGRAMMING VOLTAGE: 12.75V ± 0.25V PROGRAMMING TIME: 100µs/byte (typical) ELECTRONIC SIGNATURE – Manufacturer Code: 20h – Device Code: 3Dh 1 1 FDIP28W (F) PDIP28 (B) DESCRIPTION The M27V512 is a low voltage 512 Kbit EPROM offered in the two ranges UV (ultra viloet erase) and OTP (one time programmable). It is ideally suited for microprocessor systems and is organized as 65,536 by 8 bits. The M27V512 operates in the read mode with a supply voltage as low as 3V. The decrease in operating power allows either a reduction of the size of the battery or an increase in the time between battery recharges. The FDIP28W (window ceramic frit-seal package) has transparent lid which allows the user to expose the chip to ultraviolet light to erase the bit pattern. A new pattern can then be written to the device by following the programming procedure. For applications where the content is programmed only one time and erasure is not required, the M27V512 is offered in PDIP28, PLCC32 and TSOP28 (8 x 13.4 mm) packages. Table 1. Signal Names A0-A15 Q0-Q7 E GV PP VCC VSS Address Inputs Data Outputs Chip Enable Output Enable Supply Voltage Ground PLCC32 (K) TSOP28 (N) 8 x 13.4mm Figure 1. Logic Diagram VCC 16 A0-A15 8 Q0-Q7 E GVPP M27V512 VSS AI00732B May 1998 1/16 M27V512 Figure 2A. DIP Pin Connections Figure 2B. LCC Pin Connections AI01907 VSS DU Q3 Q4 Q5 AI00733B A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 Q0 Q1 Q2 VSS 1 28 2 27 3 26 4 25 5 24 6 23 7 22 M27V512 8 21 9 20 10 19 11 18 12 17 13 16 14 15 VCC A14 A13 A8 A9 A11 GVPP A10 E Q7 Q6 Q5 Q4 Q3 A6 A5 A4 A3 A2 A1 A0 NC Q0 A7 A12 A15 DU VCC A14 A13 1 32 A8 A9 A11 NC GVPP A10 E Q7 Q6 9 M27V512 25 17 Q1 Q2 Warning: NC = Not Connected, DU = Don’t Use Figure 2C. TSOP Pin Connections GVPP A11 A9 A8 A13 A14 VCC A15 A12 A7 A6 A5 A4 A3 22 21 28 1 M27V512 15 14 7 8 AI00734B A10 E Q7 Q6 Q5 Q4 Q3 VSS Q2 Q1 Q0 A0 A1 A2 DEVICE OPERATION The operating modes of the M27V512 are listed in the Operating Modes table. A single power supply is required in the read mode. All inputs are TTL levels except for GVPP and 12V on A9 for Electronic Signature. Read Mode The M27V512 has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (E) is the power control and should be used for device selection. Output Enable (G) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that the addresses are stable, the address access time (tAVQV) is equal to the delay from E to output (tELQV). Data is available at the output after a delay of t GLQV from the falling edge of G, assuming that E has been low and the addresses have been stable for at least tAVQV-tGLQV. Standby Mode The M27V512 has a standby mode which reduces the supply current from 10mA to 10µA with low voltage operation VCC ≤ 3.6V, see Read Mode DC Characteristics table for details.The M27V512 is placed in the standby mode by applying a CMOS high signal to the E input. When in the standby mode, the outputs are in a high impedance state, independent of the GVPP input. 2/16 M27V512 Table 2. Absolute Maximum Ratings (1) Symbol TA TBIAS TSTG VIO (2) VCC VA9 (2) VPP Parameter Ambient Operating Temperature (3) Temperature Under Bias Storage Temperature Input or Output Voltage (except A9) Supply Voltage A9 Voltage Program Supply Voltage Value –40 to 125 –50 to 125 –65 to 150 –2 to 7 –2 to 7 –2 to 13.5 –2 to 14 Unit °C °C °C V V V V Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC voltage on Output is VCC +0.5V with possible overshoot to VCC +2V for a period less than 20ns. 3. Depends on range. Table 3. Operating Modes Mode Read Output Disable Program Program Inhibit Standby Electronic Signature Note: X = VIH or VIL, VID = 12V ± 0.5V. E VIL VIL VIL Pulse V IH V IH VIL GV PP V IL VIH VPP VPP X V IL A9 X X X X X VID Q0-Q7 Data Out Hi-Z Data In Hi-Z Hi-Z Codes Table 4. Electronic Signature Identifier Manufacturer’s Code Device Code A0 VIL VIH Q7 0 0 Q6 0 0 Q5 1 1 Q4 0 1 Q3 0 1 Q2 0 1 Q1 0 0 Q0 0 1 Hex Data 20h 3Dh Two Line Output Control Because EPROMs are usually used in larger memory arrays,.


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