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EBS52UC8APFA Dataheets PDF



Part Number EBS52UC8APFA
Manufacturers Elpida Memory
Logo Elpida Memory
Description 512MB Unbuffered SDRAM DIMM
Datasheet EBS52UC8APFA DatasheetEBS52UC8APFA Datasheet (PDF)

DATA SHEET 512MB Unbuffered SDRAM DIMM EBS52UC8APFA (64M words × 64 bits, 2 banks) Description The EBS52UC8APFA is 64M words × 64 bits, 2 banks Synchronous Dynamic RAM Registered Module, mounted 16 pieces of 256M bits SDRAM sealed in TSOP package. This module provides high density and large quantities of memory in a small space without utilizing the surface mounting technology. Decoupling capacitors are mounted on power supply line for noise reduction. Features • Fully compatible with 8 bytes .

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DATA SHEET 512MB Unbuffered SDRAM DIMM EBS52UC8APFA (64M words × 64 bits, 2 banks) Description The EBS52UC8APFA is 64M words × 64 bits, 2 banks Synchronous Dynamic RAM Registered Module, mounted 16 pieces of 256M bits SDRAM sealed in TSOP package. This module provides high density and large quantities of memory in a small space without utilizing the surface mounting technology. Decoupling capacitors are mounted on power supply line for noise reduction. Features • Fully compatible with 8 bytes DIMM: JEDEC standard outline • 168-pin socket type dual in line memory module (DIMM)  PCB height: 34.93mm (1.38inch )  Lead pitch: 1.27mm • 3.3V power supply • Clock frequency: 133MHz (max.) • LVTTL interface • Data bus width: × 64 non-ECC • Single pulsed /RAS • 4 Banks can operates simultaneously and independently • Burst read/write operation and burst read/single write operation capability • Programmable burst length (BL): 1, 2, 4, 8 • 2 variations of burst sequence  Sequential  Interleave • Programmable /CAS latency (CL): 2, 3 • Byte control by DQMB • Refresh cycles: 8192 refresh cycles/64ms • 2 variations of refresh  Auto refresh  Self refresh Document No. E0208E20 (Ver. 2.0) Date Published June 2002 (K) Japan URL: http://www.elpida.com Elpida Memory, Inc. 2001-2002 EBS52UC8APFA Ordering Information Part number EBS52UC8APFA-7A EBS52UC8APFA-75* Clock frequency MHz (max.) 133 133 /CAS latency Package 2, 3 3 168-pin DIMM Contact pad Gold Mounted devices EDS2508APTA Note: 100MHz operation at /CAS latency = 2. Pin Configurations 1 pin 10 pin 11 pin 40 pin 41 pin 84 pin 85 pin 94 pin 95 pin 124 pin 125 pin 168 pin Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Pin name VSS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VDD DQ14 DQ15 NC NC VSS NC NC VDD /WE DQMB0 DQMB1 /CS0 Pin No. 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Pin name VSS NC /CS2 DQMB2 DQMB3 NC VDD NC NC NC NC VSS DQ16 DQ17 DQ18 DQ19 VDD DQ20 NC NC CKE1 VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 Pin No. 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 Pin name VSS DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VDD DQ46 DQ47 NC NC VSS NC NC VDD /CAS DQMB4 DQMB5 /CS1 Pin No. 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 Pin name VSS CKE0 /CS3 DQMB6 DQMB7 NC VDD NC NC NC NC VSS DQ48 DQ49 DQ50 DQ51 VDD DQ52 NC NC NC VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 Data Sheet E0208E20 (Ver. 2.0) 2 EBS52UC8APFA Pin No. 31 32 33 34 35 36 37 38 39 40 41 42 Pin name NC VSS A0 A2 A4 A6 A8 A10 (AP) BA1 VDD VDD CLK0 Pin No. 73 74 75 76 77 78 79 80 81 82 83 84 Pin name VDD DQ28 DQ29 DQ30 DQ31 VSS CLK2 NC NC SDA SCL VDD Pin No. 115 116 117 118 119 120 121 122 123 124 125 126 Pin name /RAS VSS A1 A3 A5 A7 A9 BA0 A11 VDD CLK1 A12 Pin No. 157 158 159 160 161 162 163 164 165 166 167 168 Pin name VDD DQ60 DQ61 DQ62 DQ63 VSS CLK3 NC SA0 SA1 SA2 VDD Pin Description Pin name A0 to A12 BA0, BA1 DQ0 to DQ63 /CS0 to /CS3 /RAS /CAS /WE DQMB0 to DQMB7 CLK0 to CLK3 CKE0, CKE1 SDA SCL SA0 to SA2 VDD VSS NC Function Address input  Row address A0 to A12  Column address A0 to A9 Bank select address Data input/output Chip select input Row enable (/RAS) input Column enable (/CAS) input Write enable input Byte data mask Clock input Clock enable input Data input/output for serial PD Clock input for serial PD Serial address input Primary positive power supply Ground No connection Data Sheet E0208E20 (Ver. 2.0) 3 EBS52UC8APFA Serial PD Matrix Byte No. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Function described Number of bytes used by module manufacturer Total SPD memory size Memory type Number of row addresses bits Number of column addresses bits Number of banks Module data width Module data width (continued) Module interface signal levels Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 1 1 0 0 1 1 0 0 0 0 0 1 1 0 0 0 0 0 1 1 1 0 0 0 1 1 0 1 0 0 1 1 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 1 0 1 1 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 1 0 0 0 0 1 0 1 1 80H 08H 04H 0DH 0AH 02H 40H 00H 01H 75H 54H 00H 82H 08H 00H 01H 8FH 04H 06H 01H 01H 00H 0EH 75H A0H 54H 60H 00H 0FH 14H 0FH 0FH 15ns 20ns 15ns 15ns 7.5ns 10ns 5.4ns 6ns Comments 128 bytes 256 bytes SDRAM 13 10 2 64 bits 0 LVTTL 7.5ns 5.4ns None. 7.8µs ×8 None. 1 CLK 1, 2, 4, 8, F 4 2, 3 0 0 SDRAM cycle time at CL = 3 0 (highest /CAS latency) SDRAM access from Clock at CL = 3 0 (highest /CAS latency) Module configuration type Refresh rate.


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