Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset/ Clear/ and Complementary Outputs
DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs
August...
Description
DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs
August 1986 Revised March 2000
DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs
General Description
This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flop on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the transition time of the falling edge of the clock pulse. Data on the J and K inputs may be changed while the clock is HIGH or LOW without affecting the outputs as long as the setup and hold times are not violated. A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the other inputs.
Ordering Code:
Order Number DM74KS112AM DM74LS112AN Package Number M16A N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
Inputs PR L H L H H H H H CLR CLK H L L H H H H H X X X ↓ ↓ ↓ ↓ H J X X X L H L H X K X X X L L H H X Q0 Q H L H (Note 1) Q0 H L Toggle Q0 Outputs Q L H H (Note 1) Q0 L H
H = HIGH Logic Level L = LOW Logic Level X = E...
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