11) Testing on application boards
When testing the IC on an application board, connecting a capacitor to a low impedance pin subjects the IC to stress.
Therefore, always discharge capacitors after each process or step. Always turn the IC's power supply off before
connecting it to or removing it from the test setup during the inspection process. Ground the IC during assembly steps
as an antistatic measure. Use similar precaution when transporting or storing the IC.
12) Switching of rotating direction (FWD/REV)
When the rotating direction is changed over by the motor rotating condition, switch the direction after the motor is
temporarily brought to the BRAKE condition or OPEN condition. It is recommended to keep the relevant conditions as
via BRAKE: Longer than braking time*.
(* the time required for the output L terminal to achieve potential below GND when brake is activated.)
13) Regarding the input pin of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements, in order to keep them
isolated. P-N junctions are formed at the intersection of these P layers with the N layers of other elements, creating a
parasitic diode or transistor. For example, the relation between each potential is as follows:
When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, as well as operating malfunctions and physical damage. Therefore, do not use methods by
which parasitic diodes operate, such as applying a voltage lower than the GND (P substrate) voltage to an input pin.
N P+ N
Other adjacent elements
Fig.17 Example of monolithic IC structure
© 2011 ROHM Co., Ltd. All rights reserved.
2011.05 - Rev.B