DSP16210

Data Sheet July 2000 DSP16210 Digital Signal Processor Features s Description The DSP16210 is the first DSP device based on the DSP16000 digital signal processing core. It is manufactured in a 0.35 µm CMOS technology and offers a 10 ns instruction cycle time at 3 V operation. Designed specifically for applications requiring a large amount of memory, a flexible DMA-based I/O structure, and high cycle efficiency, the DSP16210 is a signal coding device that can be programmed to perform a wide variety of fixed-point signal processing functions. The DSP16210 includes a mix of peripherals specifically intended to support processingintensive but cost-sensitive applications. The large on-chip RAM (60 Kwords of dual-port RAM) supports downloadable system design—a must for infrastructure applications—to support field upgrades for evolving coding standards. The DSP16210 can address up to 192 Kwords of external storage in both its code/coefficient memory address space and data memory address space. In addition, there is an internal boot ROM (IROM) that includes system boot code and hardware development system (HDS) code. This device also contains a bit manipulation unit (BMU) and a two-input, 40-bit arithmetic logic unit (ALU) with add/compare/select (ACS) for enhanced signal coding efficiency and Viterbi acceleration. To optimize I/O throughput and reduce the I/O service routine burden on the DSP core, the DSP16210 is equipped with two modular I/O units (MIOUs) that manage the simple ...