DSP1629

Data Sheet March 2000 DSP1629 Digital Signal Processor 1 Features s s Optimized for digital cellular applications with a bit manipulation unit for higher coding efficiency. On-chip, programmable, PLL clock synthesizer. 10 ns and 16.7 ns instruction cycle times at 3.0 V, and 19.2 ns and 12.5 ns instruction cycle times at 2.7 V, respectively. Mask-programmable memory map option: The DSP1629x16 features 16 Kwords on-chip dual-port RAM. The DSP1629x10 features 10 Kwords on-chip dual-port RAM. Both feature 48 Kwords on-chip ROM with a secure option. Low power consumption: — <1.9 mW/MIPS typical at 2.7 V. Flexible power management modes: — Standard sleep: 0.2 mW/MIPS at 2.7 V. — Sleep with slow internal clock: 0.7 mW at 2.7 V. — Hardware STOP (pin halts DSP): <20 µA. Mask-programmable clock options: small signal, and CMOS. 144 PBGA package (13 mm x 13 mm) available. Sequenced accesses to X and Y external memory. Object code and pin compatible with the DSP1627. Single-cycle squaring. 16 x 16-bit multiplication and 36-bit accumulation in one instruction cycle. Instruction cache for high-speed, program-efficient, zero-overhead looping. Dual 25 Mbits/s serial I/O ports with multiprocessor capability: — 16-bit data channel, 8-bit protocol channel. 8-bit parallel host interface: — Supports 8- or 16-bit transfers. — Motorola* or Intel † compatible. 8-bit control I/O interface. 256 memory-mapped I/O ports. Full-speed in-circuit emulation hardware development system on-chip. Supported by...