DSP56F801

56F801 Data Sheet Preliminary Technical Data www.DataSheet4U.com 56F800 16-bit Digital Signal Controllers DSP56F801 Rev. 16 01/2007 freescale.com www.DataSheet4U.com 56F801 General Description Up to 30 MIPS operation at 60MHz core frequency Up to 40 MIPS operation at 80MHz core frequency DSP and MCU functionality in a unified, C-efficient architecture MCU-friendly instruction set supports both DSP and controller functions: MAC, bit manipulation unit, 14 addressing modes Hardware DO and REP loops 6-channel PWM Module Two 4-channel, 12-bit ADCs Serial Communications Interface (SCI) Serial Peripheral Interface (SPI) 8K × 16-bit words (16KB) Program Flash 1K × 16-bit words (2KB) Program RAM 2K × 16-bit words (4KB) Data Flash 1K × 16-bit words (2KB) Data RAM 2K × 16-bit words (4KB) Boot Flash General Purpose Quad Timer JTAG/OnCETM port for debugging On-chip relaxation oscillator 11 shared GPIO 48-pin LQFP Package 6 PWM Outputs PWMA RESET IRQA 6 JTAG/ OnCE Port VCAPC VDD 2 4 VSS 5* Digital Reg Analog Reg VDDA VSSA Fault Input www.DataSheet4U.com 4 4 A/D1 A/D2 VREF ADC Interrupt Controller Low Voltage Supervisor Program Controller and Hardware Looping Unit Address Generation Unit Data ALU 16 x 16 + 36 → 36-Bit MAC Three 16-bit Input Registers Two 36-bit Accumulators Bit Manipulation Unit Quad Timer C Quad Timer D or GPIO Program Memory 8188 x 16 Flash 1024 x 16 SRAM Boot Flash 2048 x 16 Flash Data Memory 2048 x 16 Flash 1024...