Document
74ACT16373 16-Bit Transparent Latch with 3-STATE Outputs
August 1999 Revised October 1999
74ACT16373 16-Bit Transparent Latch with 3-STATE Outputs
General Description
The ACT16373 contains sixteen non-inverting latches with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. The flip-flops appear transparent to the data when the Latch Enable (LE) is HIGH. When LE is low, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the outputs are in high Z state.
Features
s Separate control logic for each byte s 16-bit version of the ACT373 s Outputs source/sink 24 mA s TTL-compatible inputs
Ordering Code:
Order Number 74ACT16373MEA 74ACT16373MTD Package Number MS48A MTD48 Package Description 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names OEn LEn I0–I15 O0–O15 Description Output Enable Input (Active Low) Latch Enable Input Inputs Outputs
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© 1999 Fairchild Semiconductor Corporation
DS500297
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74ACT16373
Functional Description
The ACT16373 contains sixteen D-type latches with 3STATE standard outputs. The device is byte controlled with each byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full 16-bit operation. The following description applies to each byte. When the Latch Enable (LEn) input is HIGH, data on the Dn enters the latches. In this condition the latches are transparent, i.e., a latch output will change states each time its D input changes. When LEn is LOW, the latches store information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LEn. The 3STATE standard outputs are controlled by the Output Enable (OEn) input. When OEn is LOW, the standard outputs are in the 2-state mode. When OEn is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches.
Truth Tables
Inputs LE1 X H H L OE1 H L L L Inputs LE2 X H H L OE2 H L L L I8–I15 X L H X I0–I7 X L H X Outputs O0–O7 Z L H (Previous) Outputs O8–O15 Z L H (Previous)
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance Previous = previous output prior to HIGH-to-LOW transition of LE
Logic Diagrams
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74ACT16373
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V VI = VCC + 0.5V DC Output Diode Current (IOK) VO = −0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source/Sink Current (IO) DC VCC or Ground Current per Output Pin Junction Temperature Storage Temperature +140°C −65°C to+150°C .