3-STATE Outputs. 74ACT16646 Datasheet

74ACT16646 Outputs. Datasheet pdf. Equivalent

74ACT16646 Datasheet
Recommendation 74ACT16646 Datasheet
Part 74ACT16646
Description 16-Bit Transceiver/Register with 3-STATE Outputs
Feature 74ACT16646; 74ACT16646 16-Bit Transceiver/Register with 3-STATE Outputs August 1999 Revised October 1999 74ACT.
Manufacture Fairchild Semiconductor
Datasheet
Download 74ACT16646 Datasheet




Fairchild Semiconductor 74ACT16646
August 1999
Revised October 1999
74ACT16646
16-Bit Transceiver/Register with 3-STATE Outputs
General Description
The ACT16646 contains sixteen non-inverting bidirectional
registered bus transceivers providing multiplexed transmis-
sion of data directly from the input bus or from the internal
storage registers. Each byte has separate control inputs
which can be shorted together for full 16-bit operation. The
DIR inputs determine the direction of data flow through the
device. The CPAB and CPBA inputs load data into the reg-
isters on the LOW-to-HIGH transition.
Features
s Independent registers for A and B buses
s Multiplexed real-time and stored data transfers
s Separate control logic for each byte
s 16-bit version of the ACT646
s Outputs source/sink 24 mA
s TTL-compatible inputs
Ordering Code:
Order Number Package Number
Package Description
74ACT16646SSC
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74ACT16646MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
FACTis a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation DS500345
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Fairchild Semiconductor 74ACT16646
Function Table
Inputs
Data I/O (Note 1)
G1 DIR1 CPAB1 CPBA1 SAB1 SBA1 A0–7 B0–7
Output Operation Mode
H X H or L H or L X X
Isolation
H X
X X X Input Input Clock An Data into A Register
H X X
XX
Clock Bn Data Into B Register
L H X X L X
An to Bn—Real Time (Transparent Mode)
LH
X L X Input Output Clock An Data to A Register
L H H or L X H X
LH
XHX
A Register to Bn (Stored Mode)
Clock An Data into A Register and Output to Bn
L L X X X L
Bn to An—Real Time (Transparent Mode)
LLX
X L Output Input Clock Bn Data into B Register
LL
LL
H = HIGH Voltage Level
X H or L X
XX
H
H
X = Immaterial L = LOW Voltage Level
B Register to An (Stored Mode)
Clock Bn into B Register and Output to An
 = LOW-to-HIGH Transition.
Note 1: The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled; i.e., data
at the bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs. Also applies to data I/O (A and B: 8-15) and #2 control pins.
Real Time Transfer
A-Bus to B-Bus
Storage from
Bus to Register
Real Time Transfer
B-Bus to A-Bus
Transfer from
Register to Bus
Logic Diagram
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Fairchild Semiconductor 74ACT16646
Absolute Maximum Ratings(Note 2)
Supply Voltage (VCC)
DC Input Diode Current (IIK)
VI = −0.5V
VI = VCC + 0.5V
DC Output Diode Current (IOK)
VO = −0.5V
VO = VCC + 0.5V
DC Output Voltage (VO)
DC Output Source/Sink Current (IO)
DC VCC or Ground Current
per Output Pin
Storage Temperature
0.5V to +7.0V
20 mA
+20 mA
20 mA
+20 mA
0.5V to VCC + 0.5V
±50 mA
±50 mA
65°C to +150°C
Recommended Operating
Conditions
Supply Voltage (VCC)
Input Voltage (VI)
Output Voltage (VO)
Operating Temperature (TA)
Minimum Input Edge Rate (V/t)
4.5V to 5.5V
0V to VCC
0V to VCC
40°C to +85°C
125 mV/ns
VIN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V
Note 2: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACTcircuits outside databook specifications.
DC Electrical Characteristics
Symbol
Parameter
VIH Minimum HIGH
Input Voltage
VIL Maximum LOW
Input Voltage
VOH Minimum HIGH
Output Voltage
VCC
(V)
4.5
5.5
4.5
5.5
4.5
5.5
TA = +25°C
TA = −40°C to+85°C
Typ Guaranteed Limits
1.5 2.0
2.0
1.5 2.0
2.0
1.5 0.8
0.8
1.5 0.8
0.8
4.49
4.4
4.4
5.49
5.4
5.4
VOL Maximum LOW
Output Voltage
4.5 3.86
5.5 4.86
4.5 0.001
0.1
5.5 0.001
0.1
3.76
4.76
0.1
0.1
4.5
5.5
IOZT
Maximum I/O
Leakage Current
5.5
IIN Maximum Input
Leakage Current
5.5
ICCT
ICC
Maximum ICC/Input
Max Quiescent
Supply Current
5.5 0.6
5.5
IOLD
IOHD
Minimum Dynamic
Output Current (Note 4)
5.5
Note 3: All outputs loaded; thresholds associated with output under test.
Note 4: Maximum test duration 2.0 ms; one output loaded at a time.
0.36
0.36
±0.5
±0.1
8.0
0.44
0.44
±5.0
±1.0
1.5
80.0
75
75
Units
Conditions
V VOUT = 0.1V
or VCC 0.1V
V VOUT = 0.1V
or VCC 0.1V
V IOUT = −50 µA
VIN = VIL or VIH
V IOH = 24 mA
IOH = 24 mA (Note 3)
V IOUT = 50 µA
VIN = VIL or VIH
V IOL = 24 mA
IOL = 24 mA (Note 3)
µA VIN = VIL, VIH
VO = VCC, GND
µA VI = VCC, GND
mA VI = VCC 2.1V
µA VIN = VCC or GND
mA VOLD = 1.65V Max
mA VOHD = 3.85V Min
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