WITH CLEAR. 74ACT174 Datasheet

74ACT174 CLEAR. Datasheet pdf. Equivalent

Part 74ACT174
Description HEX D-TYPE FLIP FLOP WITH CLEAR
Feature 74ACT174 HEX D-TYPE FLIP FLOP WITH CLEAR PRELIMINARY DATA s s s s s s s s s HIGH SPEED: fMA.
Manufacture STMicroelectronics
Datasheet
Download 74ACT174 Datasheet




74ACT174
74ACT174
HEX D-TYPE FLIP FLOP WITH CLEAR
s HIGH SPEED:
fMAX = 200 MHz (TYP.) at VCC = 5V
s LOW POWER DISSIPATION:
ICC = 8 µA (MAX.) at TA = 25 oC
s COMPATIBLE WITH TTL OUTPUTS
VIH = 2V (MIN), VIL = 0.8V (MAX)
s 50TRANSMISSION LINE DRIVING
CAPABILITY
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24 mA (MIN)
s BALANCED PROPAGATION DELAYS:
tPLH tPHL
s OPERATING VOLTAGE RANGE:
VCC (OPR) = 4.5V to 5.5V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 174
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The ACT174 is an high-speed CMOS HEX
D-TYPE FLIP FLOP WITH CLEAR fabricated
with sub-micron silicon gate and double-layer
metal wiring C2MOS technology. It is ideal for low
power applications mantaining high speed
operation similar to eqivalent Bipolar Schottky
PRELIMINARY DATA
BM
(Plastic Package)
(Micro Package)
ORDER CODES :
74ACT174B
74ACT174M
TTL.
Information signals applied to D inputs are
transfered to the Q output on the positive going
edge of the clock pulse.
When the CLEAR input is held low, the Q outputs
are held low independentelyof the other inputs .
The device is designed to interface directly High
Speed CMOS systems with TTL, NMOS and
CMOS output voltage levels.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
May 1997
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74ACT174
74ACT174
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
1
2, 5, 7, 10,
12, 15
3, 4, 6, 11,
13, 14
9
8
16
SYMBOL
CLEAR
Q0 to Q5
NAME AND FUNCTION
Asyncronous Master Reset
(Active LOW)
Flip-Flop Outpus
D0 to D5 Data Inputs
CLOCK
GND
VCC
Clock Input (LOW-to-HIGH,
Edge- Triggered)
Ground (0V)
Positive Supply Voltage
TRUTH TABLE
CLEAR
L
H
H
H
X: Don’t Care
INPUTS
D
X
L
H
X
LOGIC DIAGRAM
CLOCK
X
OUTPUTS
Q
L
L
H
Qn
FUNCTION
CLEAR
NO CHANGE
This logic diagram has not be used to estimate propagation delays
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