D-Type Flip-Flop. 74ACT175 Datasheet

74ACT175 Flip-Flop. Datasheet pdf. Equivalent

Part 74ACT175
Description Quad D-Type Flip-Flop
Feature 74AC175, 74ACT175 Quad D-Type Flip-Flop 74AC175, 74ACT175 Quad D-Type Flip-Flop Features ■ ICC redu.
Manufacture Fairchild Semiconductor
Datasheet
Download 74ACT175 Datasheet




74ACT175
74AC175, 74ACT175
Quad D-Type Flip-Flop
Features
ICC reduced by 50%
Edge-triggered D-type inputs
Buffered positive edge-triggered clock
Asynchronous common reset
True and complement output
Outputs source/sink 24mA
ACT175 has TTL-compatible inputs
April 2007
tm
General Description
The AC/ACT175 is a high-speed quad D-type flip-flop.
The device is useful for general flip-flop requirements
where clock and clear inputs are common. The informa-
tion on the D-type inputs is stored during the LOW-to-
HIGH clock transition. Both true and complemented out-
puts of each flip-flop are provided. A Master Reset input
resets all flip-flops, independent of the Clock or D-type
inputs, when LOW.
Ordering Information
Order
Number
Package
Number
Package Description
74AC175SC
74AC175SJ
74AC175MTC
74AC175PC
74ACT175SC
74ACT175SJ
74ACT175MTC
M16A
M16D
MTC16
N16E
M16A
M16D
MTC16
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Body
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Body
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
Connection Diagram
Pin Descriptions
Pin Names
D0–D3
CP
MR
Q0–Q3
Q0–Q3
Description
Data Inputs
Clock Pulse Input
Master Reset Input
True Outputs
Complement Outputs
FACT™ is a trademark of Fairchild Semiconductor Corporation.
©1988 Fairchild Semiconductor Corporation
74AC175, 74ACT175 Rev. 1.4
www.fairchildsemi.com



74ACT175
Logic Symbol
IEEE/IEC
Logic Diagram
Functional Description
The AC/ACT175 consists of four edge-triggered D-type
flip-flops with individual D inputs and Q and Q outputs.
The Clock and Master Reset are common. The four flip-
flops will store the state of their individual D inputs on the
LOW-to-HIGH clock (CP) transition, causing individual Q
and Q outputs to follow. A LOW input on the Master
Reset (MR) will force all Q outputs LOW and Q outputs
HIGH independent of Clock or Data inputs. The AC/
ACT175 is useful for general logic applications where a
common Master Reset and Clock are acceptable.
Truth Table
Inputs @ tn, MR = H
Dn
L
H
Outputs @ tn+1
Qn Qn
LH
HL
H = HIGH Voltage Level
L = LOW Voltage Level
tn = Bit Time before Clock Pulse
tn+1 = Bit Time after Clock Pulse
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
Figure 1.
©1988 Fairchild Semiconductor Corporation
74AC175, 74ACT175 Rev. 1.4
2
www.fairchildsemi.com







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