Document
74ACQ240 • 74ACTQ240 Quiet Series Octal Buffer/Line Driver with 3-STATE Outputs
July 1989 Revised November 1999
74ACQ240 • 74ACTQ240 Quiet Series Octal Buffer/Line Driver with 3-STATE Outputs
General Description
The ACQ/ACTQ240 is an inverting octal buffer and line driver designed to be employed as a memory address driver, clock driver and bus oriented transmitter or receiver which provides improved PC board density. The ACQ/ ACTQ utilizes Fairchild’s Quiet Series technology to guarantee quiet output switching and improve dynamic threshold performance. FACT Quiet Series features GTO output control and undershoot corrector in addition to a split ground bus for superior performance.
Features
s ICC and IOZ reduced by 50% s Guaranteed simultaneous switching noise level and dynamic threshold performance s Guaranteed pin-to-pin skew AC performance s Improved latch-up immunity s Inverting 3-STATE outputs drive bus lines or buffer memory address registers s Outputs source/sink 24 mA s Faster prop delays than the standard ACT240
Ordering Code:
Order Number 74ACQ240SC 74ACQ240SJ 74ACQ240PC 74ACTQ240SC 74ACTQ240SJ 74ACTQ240QSC Package Number M20B M20D N20A M20B M20D MQA20 Package Description 20-Lead Small Outline Integrated Circuit (SOIC)JEDEC MS-013, 0.300” Wide Body 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide 20-Lead Small Outline Integrated Circuit (SOIC)JEDEC MS-013, 0.300” Wide Body 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names OE1, OE2 I0–I7 O0–O7 Description 3-STATE Output Enable Inputs Inputs Outputs
FACT, Quiet Series, FACT Quiet Series, and GTO are trademarks of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation
DS010234
www.fairchildsemi.com
74ACQ240 • 74ACTQ240
Logic Symbol
IEEE/IEC
Truth Tables
Inputs OE1 L L H Inputs OE2 L L H
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance
Outputs In L H X (Pins 12, 14, 16, 18) H L Z Outputs In L H X (Pins 3, 5, 7, 9) H L Z
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74ACQ240 • 74ACTQ240
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) DC Latch-Up Source or Sink Current Junction Temperature (TJ) PDIP 140°C ±300 mA ±50 mA −65°C to +150 °C ±50 mA −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V −0.5V to +7.0V
Recommended Operating Conditions
Supply Voltage (VCC) ACQ ACTQ Input Voltage (VI) Output Voltage (VO) Operating Temperature .