NAND gate. 74AHC00 Datasheet

74AHC00 gate. Datasheet pdf. Equivalent


NXP 74AHC00
INTEGRATED CIRCUITS
DATA SHEET
74AHC00; 74AHCT00
Quad 2-input NAND gate
Product specification
Supersedes data of 1998 Dec 09
File under Integrated Circuits, IC06
1999 Sep 23


74AHC00 Datasheet
Recommendation 74AHC00 Datasheet
Part 74AHC00
Description Quad 2-input NAND gate
Feature 74AHC00; INTEGRATED CIRCUITS DATA SHEET 74AHC00; 74AHCT00 Quad 2-input NAND gate Product specification Super.
Manufacture NXP
Datasheet
Download 74AHC00 Datasheet




NXP 74AHC00
Philips Semiconductors
Quad 2-input NAND gate
Product specification
74AHC00; 74AHCT00
FEATURES
ESD protection:
HBM EIA/JESD22-A114-A
exceeds 2000 V
MM EIA/JESD22-A115-A
exceeds 200 V
CDM EIA/JESD22-C101
exceeds 1000 V
Balanced propagation delays
All inputs have Schmitt-trigger
actions
Inputs accept voltages higher than
VCC
For AHC only:
operates with CMOS input levels
For AHCT only:
operates with TTL input levels
Specified from
40 to +85 and +125 °C.
DESCRIPTION
The 74AHC/AHCT00 are high-speed
Si-gate CMOS devices and are pin
compatible with low power Schottky
TTL (LSTTL).
They are specified in compliance with
JEDEC standard No. 7A.
The 74AHC/AHCT00 provides the
2-input NAND function.
FUNCTION TABLE
See note 1.
INPUT
nA
L
L
H
H
Note
1. H = HIGH voltage level;
L = LOW voltage level.
nB
L
H
L
H
OUTPUT
nY
H
H
H
L
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf 3.0 ns.
SYMBOL PARAMETER
CONDITIONS
TYPICAL
UNIT
AHC AHCT
tPHL/tPLH propagation delay CL = 15 pF;
nA, nB to nY
VCC = 5 V
3.2 3.3 ns
CI input capacitance VI = VCC or GND 3.0 3.0 pF
CO output capacitance
4.0 4.0 pF
CPD power dissipation CL = 50 pF; 7.0 7.0 pF
capacitance
f = 1 MHz;
notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
(CL × VCC2 × fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in Volts.
2. The condition is VI = GND to VCC.
PINNING
PIN
1, 4, 9 and 12
2, 5, 10 and 13
3, 6, 8 and 11
7
14
SYMBOL
1A to 4A
1B to 4B
1Y to 4Y
GND
VCC
DESCRIPTION
data inputs
data inputs
data outputs
ground (0 V)
DC supply voltage
1999 Sep 23
2



NXP 74AHC00
Philips Semiconductors
Quad 2-input NAND gate
ORDERING INFORMATION
OUTSIDE NORTH
AMERICA
NORTH AMERICA
74AHC00D
74AHC00PW
74AHCT00D
74AHCT00PW
74AHC00D
74AHC00PW DH
74AHCT00D
74AHCT00PW DH
PINS
14
14
14
14
Product specification
74AHC00; 74AHCT00
PACKAGES
PACKAGE
MATERIAL
SO
TSSOP
SO
TSSOP
plastic
plastic
plastic
plastic
CODE
SOT108-1
SOT402-1
SOT108-1
SOT402-1
handbook, halfpage
1A 1
1B 2
1Y 3
2A 4
2B 5
2Y 6
GND 7
14 VCC
13 4B
12 4A
00 11 4Y
10 3B
9 3A
8 3Y
MNA210
Fig.1 Pin configuration.
handbook, halfpage
1 1A
2 1B
4 2A
5 2B
9 3A
10 3B
12 4A
13 4B
1Y 3
2Y 6
3Y 8
4Y 11
MNA212
Fig.3 Functional diagram.
1999 Sep 23
handbook, halfpage A
B
Y
MNA211
Fig.2 Logic diagram (one gate).
handbook, halfpage
1
&
2
3
4
&
5
6
9
&
10
8
12 & 11
13
MNA246
Fig.4 IEC logic symbol.
3







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