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74AHCT1G79 Dataheets PDF



Part Number 74AHCT1G79
Manufacturers NXP
Logo NXP
Description Single D-type flip-flop; positive-edge trigger
Datasheet 74AHCT1G79 Datasheet74AHCT1G79 Datasheet (PDF)

INTEGRATED CIRCUITS DATA SHEET 74AHC1G79; 74AHCT1G79 Single D-type flip-flop; positive-edge trigger Product specification File under Integrated Circuits, IC06 1999 May 18 Philips Semiconductors Product specification Single D-type flip-flop; positive-edge trigger FEATURES • Symmetrical output impedance • High noise immunity • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V; MM EIA/JESD22-A115-A exceeds 200 V • Low power dissipation • Balanced propagation delays • Very small 5 pin package • .

  74AHCT1G79   74AHCT1G79



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INTEGRATED CIRCUITS DATA SHEET 74AHC1G79; 74AHCT1G79 Single D-type flip-flop; positive-edge trigger Product specification File under Integrated Circuits, IC06 1999 May 18 Philips Semiconductors Product specification Single D-type flip-flop; positive-edge trigger FEATURES • Symmetrical output impedance • High noise immunity • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V; MM EIA/JESD22-A115-A exceeds 200 V • Low power dissipation • Balanced propagation delays • Very small 5 pin package • Output capability: standard. DESCRIPTION The 74AHC1G/AHCT1G79 is a high-speed Si-gate CMOS device. The 74AHC1G/AHCT1G79 provides a single positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. FUNCTION TABLE See note 1. INPUTS CP ↑ ↑ L Note 1. H = HIGH voltage level; L = LOW voltage level; ↑ = LOW-to-HIGH CP transition; X = don’t care; Q + 1 = state after the next LOW-to-HIGH CP transition. D L H X OUTPUT Q+1 L H Q Notes QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf ≤ 3.0 ns. 74AHC1G79; 74AHCT1G79 TYPICAL SYMBOL tPHL/tPLH CI CPD PARAMETER propagation delay CP to Q input capacitance power dissipation capacitance CONDITIONS AHC1G CL = 15 pF; VCC = 5 V 3.5 1.5 notes 1 and 2; 15 CL = 50 pF; f = 1 Mhz AHCT1G 3.5 1.5 16 ns pF pF UNIT 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V. 2. The condition is VI = GND to VCC. PINNING PIN 1 2 3 4 5 SYMBOL D CP GND Q VCC data input clock pulse input ground (0 V) data output DC supply voltage DESCRIPTION 1999 May 18 2 Philips Semiconductors Product specification Single D-type flip-flop; positive-edge trigger ORDERING AND PACKAGE INFORMATION PACKAGES TYPE NUMBER 74AHC1G79GW 74AHCT1G79GW TEMPERATURE RANGE −40 to +85 °C PINS 5 5 PACKAGE SC-88A SC-88A MATERIAL plastic plastic 74AHC1G79; 74AHCT1G79 CODE SOT353 SOT353 MARKING AP CP fpage fpage D 1 CP 2 GND 3 MNA439 5 VCC fpage 1 D Q 4 79 4 Q 2 CP MNA440 1 2 MNA441 4 Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol. handbook, full pagewidth CP C C C C D TG C TG C Q C C TG TG C C MNA442 Fig.4 Logic diagram. 1999 May 18 3 Philips Semiconductors Product specification Single D-type flip-flop; positive-edge trigger RECOMMENDED OPERATING CONDITIONS 74AHC1G SYMBOL VCC VI VO Tamb PARAMETER DC supply voltage input voltage output voltage operating ambient temperature range input rise and fall times except for Schmitt-trigger inputs see DC and AC characteristics per device VCC = 3.3 V ±0.3 V VCC = 5 V ±0.5 V CONDITIONS MIN. 2.0 0 0 −40 TYP. 5.0 − − +25 MAX. 5.5 5.5 VCC +85 MIN. 4.5 0 0 −40 74AHC1G79; 74AHCT1G79 74AHCT1G UNIT TYP. 5.


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