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74ALS161B Dataheets PDF



Part Number 74ALS161B
Manufacturers NXP
Logo NXP
Description 4-bit binary counter
Datasheet 74ALS161B Datasheet74ALS161B Datasheet (PDF)

INTEGRATED CIRCUITS 74ALS161B/74ALS163B 4-bit binary counter Product specification IC05 Data Handbook 1991 Feb 08 Philips Semiconductors Philips Semiconductors Product specification 4-bit binary counter 74ALS161B 74ALS163B FEATURES 74ALS161B/74ALS163B 4-bit binary counter, asynchronous reset 4-bit binary counter, synchronous reset DESCRIPTION Synchronous presettable 4-bit binary counters (74ALS161B, 74ALS163B) feature an internal carry look-ahead and can be used for high speed counting. S.

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INTEGRATED CIRCUITS 74ALS161B/74ALS163B 4-bit binary counter Product specification IC05 Data Handbook 1991 Feb 08 Philips Semiconductors Philips Semiconductors Product specification 4-bit binary counter 74ALS161B 74ALS163B FEATURES 74ALS161B/74ALS163B 4-bit binary counter, asynchronous reset 4-bit binary counter, synchronous reset DESCRIPTION Synchronous presettable 4-bit binary counters (74ALS161B, 74ALS163B) feature an internal carry look-ahead and can be used for high speed counting. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock. The clock input is buffered. The outputs of the counters may be preset to High or Low level. A Low level at the parallel enable (PE) input disables the counting action and causes the data at the D0 – D3 inputs to be loaded into the counter on the positive-going edge of the clock (provided that the setup and hold requirements for PE are met). Preset takes place regardless of the levels at count enable (CEP, CET) inputs. A Low level at the master reset (MR) input sets all the four outputs of the flip-flops (Q0 – Q3) in 74ALS161B to Low levels, regardless of the levels at CP, PE, CET and CEP inputs (thus providing an asynchronous clear function). For the 74ALS163B the clear function is synchronous. A Low level at the synchronous reset (SR) input sets all four outputs of the flip-flops (Q0 – Q3) to Low levels after the next positive-going transition on the clock (CP) input ( provided that the setup and hold time requirements for SR are met). This action occurs regardless of the levels at CP, PE, CET and CEP inputs. The synchronous reset feature enables the designer to modify the maximum count with only one external NAND gate (see Figure 1). The carry look-ahead simplifies serial cascading of the counters. Both count enable (CEP and CET) inputs must be High to count. The CET input is fed forward to enable the TC output. The TC output thus enabled will produce a High output pulse of a duration approximately equal to the High level output of Q0. This pulse can be used to enable the next cascaded stage (see Figure 2). The TC output is subjected to decoding spikes due to internal race conditions, Therefore, it is not recommended for use as clock or asynchronous reset for flip-flops, registers, or counters. • Synchronous counting and loading • Two count enable inputs for n-bit cascading • Positive edge-triggered clock • Asynchronous reset (74ALS161B) • Synchronous reset (74ALS163B) • High speed synchronous expansion • Typical count rate of 140MHz TYPICAL SUPPLY CURRENT (TOTAL) 10mA 10mA TYPE 74ALS161B 74ALS163B TYPICAL fMAX 140MHz 140MHz ORDERING INFORMATION ORDER CODE DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C 74ALS161BN, 74ALS163BN 74ALS161BD, 74ALS163BD 74ALS161BDB, 74ALS163BDB DRAWING NUMBER SOT38-4 SOT109-1 SOT338-1 16-pin plastic DIP 16-pin plastic SO 16-pin plastic SSOP Type II INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS D0 – D3 CEP CET CP PE MR SR Q0 – Q3 TC Data inputs Count enable parallel input (active-Low) Count enable trickle input (active-Low) Clock input (active rising edge) Parallel enable input (active-Low) Asynchronous master reset input (active-Low) for 74ALS161B Asynchronous reset input (active-Low) for 74ALS163B Flip-flop outputs Terminal count output (active-Low) DESCRIPTION 74ALS (U.L.) HIGH/LOW 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 20/80 20/80 LOAD VALUE HIGH/LOW 20µA/0.1mA 20µA/0.1mA 20µA/0.1mA 20µA/0.1mA 20µA/0.1mA 20µA/0.1mA 20µA/0.1mA 0.4mA/8mA 0.4mA/8mA NOTE: One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1mA in the Low state. 1991 Feb 08 2 853–1350 01670 Philips Semiconductors Product specification 4-bit binary counter 74ALS161B/74ALS163B STATE DIAGRAM 0 1 2 3 4 15 5 14 6 13 7 12 11 10 9 8 SF00664 APPLICATIONS VCC PE CEP CET CLOCK CP SR D0 D1 D2 D3 74ALS163B TC Q0 Q1 Q2 Q3 SC00086 Figure 1. Maximum Count Modifying Scheme Terminal Count = 6 H H = Enable count or L L = Disable count D0 D1 D2 D3 PE CEP 74ALS163B CET TC CP SR Q0 Q1 Q2 Q3 D0 D1 D2 D3 PE CEP 74ALS163B CET TC CP SR Q0 Q1 Q2 Q3 D0 D1 D2 D3 PE CEP 74ALS163B CET TC CP SR Q0 Q1 Q2 Q3 D0 D1 D2 D3 PE CEP 74ALS163B CET TC CP SR Q0 Q1 Q2 Q3 D0 D1 D2 D3 PE CEP 74ALS163B CET TC CP SR Q0 Q1 Q2 Q3 CP SC00087 Figure 2. Synchronous Multistage Counting Scheme 1991 Feb 08 3 Philips Semiconductors Product specification 4-bit binary counter 74ALS161B/74ALS163B PIN CONFIGURATION – 74ALS161B MR CP D0 D1 D2 D3 CEP GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC TC Q0 Q1 Q2 Q3 CET PE PIN CONFIGURATION – 74ALS163B SR CP D0 D1 D2 D3 CEP GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC TC Q0 Q1 Q2 Q3 CET PE SF00656 SF00657 LOGIC SYMBOL – 74ALS161B 3 4 5 6 LOGIC SYMBOL – 74ALS163B 3 4 5 6 9 7 10 2 1 PE CEP CET CP MR D0 D1 D2 D3 9 7 TC 15 10 2 PE CEP CET CP SR D0 D1 D2 D3 TC 15 Q0 Q1 Q2 Q3 1 Q0 Q1 Q2 .


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