74ALS273

INTEGRATED CIRCUITS 74ALS273 Octal D–type flip–flop Product specification IC05 Data Handbook 1991 Feb 08 Philips Semiconductors Philips Semiconductors Product specification Octal D-type flip-flop 74ALS273 FEATURES Eight edge-triggered D-type flip-flops Buffered common clock Buffered asynchronous master reset See 74ALS377 for clock enable version See 74ALS373 for transparent latch version See 74ALS374 for 3-State version DESCRIPTION The 74ALS273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered clock (CP) and master reset (MR) inputs load and reset all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup time before the Low-to-High clock transition, is transferred to the corresponding flip-flop’s Q output. All outputs will be forced Low independently of clock or data inputs by a Low voltage level on the MR input. The device is useful for applications where the true output only is required and the CP and MR are common to all flip-flops. TYPICAL SUPPLY CURRENT (TOTAL) 16mA PIN CONFIGURATION MR Q0 D0 D1 Q1 Q2 D2 D3 Q3 1 2 3 4 5 6 7 8 9 20 19 18 17 16 15 14 13 12 11 VCC Q7 D7 D6 Q6 Q5 D5 D4 Q4 CP GND 10 SF00346 ORDERING INFORMATION ORDER CODE DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C 74ALS273N 74ALS273D 74ALS273DB DRAWING NUMBER 20-pin plastic DIP 20-pin plastic SO 20-pin plastic SSOP Type II SOT146-1 SOT163-1 SOT339-1 TYPE 74ALS273...