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74ALVC16501 Dataheets PDF



Part Number 74ALVC16501
Manufacturers Fairchild Semiconductor
Logo Fairchild Semiconductor
Description Low Voltage 18-Bit Universal Bus Transceivers
Datasheet 74ALVC16501 Datasheet74ALVC16501 Datasheet (PDF)

74ALVC16501 Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs October 2001 Revised October 2001 74ALVC16501 Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs General Description The ALVC16501 is an 18-bit universal bus transceiver which combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-en.

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74ALVC16501 Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs October 2001 Revised October 2001 74ALVC16501 Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs General Description The ALVC16501 is an 18-bit universal bus transceiver which combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB is held at a HIGH or LOW logic level. If LEAB is LOW, the A bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CLKAB. When OEAB is HIGH, the outputs are active. When OEAB is LOW, the outputs are in a highimpedance state. Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, and CLKBA. The output enables are complementary (OEAB is active HIGH and OEBA is active LOW). The ALVC16501 is designed for low voltage (1.65V to 3.6V) VCC applications with I/O capability up to 3.6V. The ALVC16501 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation. Features s 1.65V–3.6V VCC supply operation s 3.6V tolerant inputs and outputs s tPD (A to B, B to A) 3.4 ns max for 3.0V to 3.6V VCC 4.0 ns max for 2.3V to 2.7V VCC 7.0 ns max for 1.65V to 1.95V VCC s Power-down high impedance inputs and outputs s Supports live insertion/withdrawal (Note 1) s Uses patented noise/EMI reduction circuitry s Latchup conforms to JEDEC JED78 s ESD performance: Human body model > 2000V Machine model >200V Note 1: To ensure the high-impedance state during power up or power down, OEBA should be tied to VCC through a pull-up resistor and OEAB should be tied to GND through a pull-down resistor; the minimum value of the resistors is determined by the current-sourcing capability of the driver. Ordering Code: Order Number 74ALVC16501MTD Package Number MTD56 Package Description 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 2001 Fairchild Semiconductor Corporation DS500683 www.fairchildsemi.com 74ALVC16501 Connection Diagram Pin Descriptions Pin Names OEAB OEBA LEAB, LEBA CLKAB, CLKBA A1–A18 B1–B18 Description Output Enable Input for A to B Direction (Active HIGH) Output Enable Input for B to A Direction (Active LOW) Latch Enable Inputs Clock Inputs Side A Inputs or 3-STATE Outputs Side B Inputs or 3-STATE Outputs Function Table (Note 2) Inputs OEAB L H H H H H H LEAB X H H L L L L CLKAB X X X An X L H L H X X Outputs Bn Z L H L H B0 (Note 3) B0 (Note 4) ↑ ↑ H L H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial (HIGH or LOW, inputs may not float) Z = High Impedance Note 2: A-to-B data flow is shown; B-to-A flow is similar but uses OEBA, LEBA and CLKBA. OEBA is active LOW. Note 3: Output level before the indicated steady-state input conditions were established. Note 4: Output level before the indicated steady-state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW. www.fairchildsemi.com 2 74ALVC16501 Logic Diagram 3 www.fairchildsemi.com 74ALVC16501 Absolute Maximum Ratings(Note 5) Supply Voltage (VCC) DC Input Voltage (VI) Output Voltage (VO) (Note 6) DC Input Diode Current (IIK) VI < 0V DC Output Diode Current (IOK) VO < 0V DC Output Source/Sink Current (IOH/IOL) DC VCC or GND Current per Supply Pin (I CC or GND) Storage Temperature Range (TSTG) −0.5V to +4.6V −0.5V to 4.6V −0.5V to VCC +0.5V −50 mA −50 mA ±50 mA ±100 mA −65°C to +150°C Recommended Operating Conditions (Note 7) Power Supply Operating Input Voltage (VI) Output Voltage (VO) Free Air Operating Temperature (TA) Minimum Input Edge Rate (∆t/∆V) VIN = 0.8V to 2.0V, VCC = 3.0V 10 ns/V Note 5: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 6: IO Absolute Maximum Rating must be observed. Note 7: Floating or unused inputs must be held HIGH or LOW. 1.65V to 3.6V 0V to VCC 0V to VCC −40°C to +85°C DC Electrical Characteristics Symbol VIH Parameter HIGH Level Input Voltage Conditions VCC (V) 1.65 -1.95 2.3 - 2.7 2.7 - 3.6 VIL LOW Level Input Voltage 1.65 -1.95 2.3 - 2.7 2.7 - 3.6 VOH HIGH Level Output Voltage IOH = −100 µA IOH = −4 mA IOH = −6 mA IOH = −12 mA 1.65 - 3.6 1.65 2.3 2.3 2.7 3.0 IOH = −24 mA VOL LOW Level Output Voltage IOL = 100 µA IOL = 4 mA IOL = 6 mA IOL = 12mA.


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