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74ALVCH162244 Dataheets PDF



Part Number 74ALVCH162244
Manufacturers Fairchild Semiconductor
Logo Fairchild Semiconductor
Description Low Voltage 16-Bit Buffer/Line Driver
Datasheet 74ALVCH162244 Datasheet74ALVCH162244 Datasheet (PDF)

74ALVCH162244 Low Voltage 16-Bit Buffer/Line Driver with Bushold and 26Ω Series Resistor in Outputs September 2001 Revised February 2002 74ALVCH162244 Low Voltage 16-Bit Buffer/Line Driver with Bushold and 26Ω Series Resistor in Outputs General Description The ALVCH162244 contains sixteen non-inverting buffers with 3-STATE outputs to be employed as a memory and address driver, clock driver, or bus oriented transmitter/ receiver. The device is nibble (4-bit) controlled. Each nibble has separate.

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74ALVCH162244 Low Voltage 16-Bit Buffer/Line Driver with Bushold and 26Ω Series Resistor in Outputs September 2001 Revised February 2002 74ALVCH162244 Low Voltage 16-Bit Buffer/Line Driver with Bushold and 26Ω Series Resistor in Outputs General Description The ALVCH162244 contains sixteen non-inverting buffers with 3-STATE outputs to be employed as a memory and address driver, clock driver, or bus oriented transmitter/ receiver. The device is nibble (4-bit) controlled. Each nibble has separate 3-STATE control inputs which can be shorted together for full 16-bit operation. The ALVCH162244 data inputs include active bushold circuitry, eliminating the need for external pull-up resistors to hold unused or floating data inputs at a valid logic level The 74ALVCH162244 is also designed with 26Ω series resistors in the outputs. This design reduces line noise in applications such as memory address drivers, clock drivers, and bus transceivers/transmitters. The 74ALVCH162244 is designed for low voltage (1.65V to 3.6V) VCC applications with output capability up to 3.6V. The 74ALVCH162244 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation. Features s 1.65V to 3.6V VCC supply operation s 3.6V tolerant control inputs and outputs s Bushold on data inputs eliminates the need for external pull-up/pull-down resistors s 26Ω series resistors in outputs s tPD 4.2 ns max for 3.0V to 3.6V VCC 4.9 ns max for 2.3V to 2.7V VCC 7.6 ns max for 1.65V to 1.95V VCC s Uses patented noise/EMI reduction circuitry s Latch-up conforms to JEDEC JED78 s ESD performance: Human body model > 2000V Machine model > 200V Ordering Code: Order Number 74ALVCH162244T Package Number MTD48 Package Description 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Pin Descriptions Pin Names OEn I0–I15 O0–O15 Description Output Enable Input (Active LOW) Bushold Inputs Outputs © 2002 Fairchild Semiconductor Corporation DS500632 www.fairchildsemi.com 74ALVCH162244 Connection Diagram Truth Tables Inputs OE1 L L H Inputs OE2 L L H Inputs OE3 L L H Inputs OE4 L L H L H X I12–I15 L H Z L H X I8–I11 L H Z Outputs O12–O15 L H X I4–I7 L H Z Outputs O8–O11 I0–I3 L H X Outputs O4–O7 Outputs O0–O3 L H Z H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial (HIGH or LOW, inputs may not float) Z = High Impedance Functional Description The 74ALVCH162244 contains sixteen non-inverting buffers with 3-STATE outputs. The device is nibble (4 bits) controlled with each nibble functioning identically, but independent of each other. The control pins may be shorted together to obtain full 16-bit operation.The 3-STATE outputs are controlled by an Output Enable (OEn) input. When OEn is LOW, the outputs are in the 2-state mode. When OEn is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the inputs. Logic Diagram www.fairchildsemi.com 2 74ALVCH162244 Absolute Maximum Ratings(Note 1) Supply Voltage (VCC) DC Input Voltage (VI) Output Voltage (VO) (Note 2) DC Input Diode Current (IIK) VI < 0V DC Output Diode Current (IOK) VO < 0V DC Output Source/Sink Current (IOH/IOL) DC VCC or GND Current per Supply Pin (ICC or GND) Storage Temperature Range (TSTG) −0.5V to +4.6V −0.5V to 4.6V −0.5V to VCC +0.5V −50 mA −50 mA ±50 mA ±100 mA −65°C to +150°C Recommended Operating Conditions (Note 3) Power Supply Operating Input Voltage Output Voltage (VO) Free Air Operating Temperature (TA) Minimum Input Edge Rate (∆t/∆V) VIN = 0.8V to 2.0V, VCC = 3.0V 10 ns/V Note 1: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 2: IO Absolute Maximum Rating must be observed. Note 3: Floating or unused control inputs must be held HIGH or LOW. 1.65V to 3.6V 0V to VCC 0V to VCC −40°C to +85°C DC Electrical Characteristics Symbol VIH Parameter HIGH Level Input Voltage Conditions VCC (V) 1.65 - 1.95 2.3 - 2.7 2.7 - 3.6 VIL LOW Level Input Voltage 1.65 - 1.95 2.3 - 2.7 2.7 - 3.6 VOH HIGH Level Output Voltage IOH = −100 µA IOH = −2 mA IOH = −4 mA IOH = −6 mA IOH = −8 mA IOH = −12 mA VOL LOW Level Output Voltage IOL = 100 µA IOL = 2 mA IOL = 4 mA IOL = 6 mA IOL = 8 mA IOL = 12 mA II II(HOLD) Input Leakage Current Bushold Input Minimum Drive Hold Current 0 ≤ VI ≤ 3.6V VIN = 0.58V VIN = 1.07V VIN = 0.7V VIN = 1.7V VIN = 0.8V VIN = 2.0V 0 < VO ≤ 3.6V IOZ ICC ∆ICC 3-STATE Output Leakage Quiescent Supply Current Increase in ICC per Input 0 ≤ VO ≤ 3.6V VI = V CC or GND, IO = 0 VIH = VCC − 0.6V 1.65 - .


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