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74ALVCH162245 Dataheets PDF



Part Number 74ALVCH162245
Manufacturers Integrated Device Technology
Logo Integrated Device Technology
Description 3.3V CMOS 16-BIT BUS TRANSCIEVER
Datasheet 74ALVCH162245 Datasheet74ALVCH162245 Datasheet (PDF)

IDT74ALVCH162245 3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 16-BIT BUS TRANSCIEVER WITH 3-STATE OUTPUTS AND BUS-HOLD .EATURES: • 0.5 MICRON CMOS Technology • Typical tSK(o) (Output Skew) < 250ps • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range • VCC = 2.5V ± 0.2V • CMOS power levels (0.4µ W typ. static) • Rail-to-Rail output swing for.

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IDT74ALVCH162245 3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 16-BIT BUS TRANSCIEVER WITH 3-STATE OUTPUTS AND BUS-HOLD .EATURES: • 0.5 MICRON CMOS Technology • Typical tSK(o) (Output Skew) < 250ps • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range • VCC = 2.5V ± 0.2V • CMOS power levels (0.4µ W typ. static) • Rail-to-Rail output swing for increased noise margin • Available in SSOP, TSSOP, and TVSOP packages IDT74ALVCH162245 DESCRIPTION: This 16-bit bus transceiver is built using advanced dual metal CMOS technology. The ALVCH162245 is designed for asynchronous communication between data buses. The control-function implementation minimizes external timing requirements. This device can be used as two 8-bit transceivers or one 16-bit transceiver. It allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated. The ALVCH162245 has series resistors in the device out-put structure of the “A” port which will significantly reduce line noise when used with light loads. This driver has been designed to drive ±12mA at the designated threshold levels. The “B” port has a ±24mA driver. The ALVCH162245 has “bus-hold” which retains the inputs’ last state whenever the input bus goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors. DRIVE .EATURES: • Balanced Output Drivers: ±12mA (A port) • High Output Drivers: ±24mA (B port) APPLICATIONS: • 3.3V high speed systems • 3.3V and lower voltage computing systems .UNCTIONAL BLOCK DIAGRAM 1 D IR 1 2 D IR 48 24 25 1 OE 1A 1 47 2 46 3 44 5 43 6 41 8 40 9 38 11 2 OE 2A 1 1B 1 2A 2 1B 2 2A 3 1B 3 2A 4 1B 4 2A 5 1B 5 2A 6 1B 6 2A 7 1B 7 2A 8 12 36 13 35 14 33 16 32 17 30 19 29 20 27 22 2B 1 1A 2 2B 2 1A 3 2B 3 1A 4 2B 4 1A 5 2B 5 1A 6 2B 6 1A 7 2B 7 1A 8 37 26 1B 8 23 2B 8 The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE 1 © 1999 Integrated Device Technology, Inc. APRIL 1999 DSC-4748/1 IDT74ALVCH162245 3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE PIN CON.IGURATION ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM(2) VTERM(3) TSTG IOUT IIK IOK ICC ISS Description Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Storage Temperature DC Output Current Continuous Clamp Current, VI < 0 or VI > VCC Continuous Clamp Current, VO < 0 Continuous Current through each VCC or GND Max –0.5 to +4.6 –0.5 to VCC+0.5 –65 to +150 –50 to +50 ±50 –50 ±100 Unit V V °C mA mA mA mA 1 DIR 1B 1 1B 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 OE 1A 1 1A 2 GND 1B 3 1B 4 GND 1A 3 1A 4 V CC 1B 5 1B 6 V CC 1A 5 1A 6 GND 1B 7 1B 8 2B 1 2B 2 GND 1A 7 1A 8 2A 1 2A 2 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminals. 3. All terminals except VCC. CAPACITANCE (TA = +25°C, F = 1.0MHz) Symbol CIN COUT CI/O Parameter(1) Input Capacitance Output Capacitance I/O Port Capacitance Conditions VIN = 0V VOUT = 0V VIN = 0V Typ. 5 7 7 Max. 7 9 9 Unit pF pF pF GND 2B 3 2B 4 GND 2A 3 2A 4 NOTE: 1. As applicable to the device type. V CC 2B 5 2B 6 V CC 2A 5 2A 6 PIN DESCRIPTION Pin Names x OE DIR xAx(1) xBx(1) Description Output Enable Inputs (Active LOW) Direction Control Inputs Side A Inputs or 3-State Outputs Side B Inputs or 3-State Outputs GND 2B 7 2B 8 2 DIR GND 2A 7 2A 8 2 OE NOTE: 1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os. SSOP/ TSSOP/ TVSOP TOP VIEW .UNCTION TABLE (EACH 8-BIT SECTION)(1) Inputs xOE L L H NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care xDIR L H X Outputs B data to A bus A data to B bus Isolation 2 IDT74ALVCH162245 3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = –40°C to +85°C Symbol VIH Parameter Input HIGH Voltage Level VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VIL IIH IIL IOZH IOZL VIK VH ICCL ICCH ICCZ ∆ICC Input LOW Voltage Level Input HIGH Current Input LOW Current High Impedance Output Current (3-State Output pins) Clamp Diode Voltage Input Hysteresis Quiescent.


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