74ALVCH16652

INTEGRATED CIRCUITS DATA SHEET 74ALVCH16652 16-bit transceiver/register with dual enable; 3-state Product specification Supersedes data of 1998 Aug 31 File under Integrated Circuits, IC24 1999 Nov 23 Philips Semiconductors Product specification 16-bit transceiver/register with dual enable; 3-state FEATURES In accordance with JEDEC standard no. 8-1A CMOS low power consumption MULTIBYTE™ flow-through pin-out architecture Low inductance, multiple supply and ground pins for minimum noise and ground bounce Direct interface with TTL levels All data inputs have bus hold Output drive capability 50 Ω transmission lines at 85 °C Current drive ±24 mA at 3.0 V. DESCRIPTION The 74ALVCH16652 consists of 16 non-inverting bus transceiver circuits with 3-state outputs, D-type flip-flops and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. Data on the ‘A’ or ‘B’, or both buses, will be stored in the internal registers, at the appropriate clock inputs (nCPAB or nCPBA) regardless of the select inputs (nSAB and nSBA) or output enable (nOEAB and nOEBA) control inputs. QUICK REFERENCE DATA Ground = 0; Tamb = 25 °C; tr = tf = 2.5 ns. SYMBOL tPHL/tPLH fmax CI CPD PARAMETER propagation delay nAn, nBn to nBn, nAn maximum clock frequency input capacitance power dissipation capacitance per latch notes 1 and 2 outputs enabled outputs disabled Notes 1. CPD is used to determine the dynamic power dissipation ...