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74ALVCH16827 Dataheets PDF



Part Number 74ALVCH16827
Manufacturers NXP
Logo NXP
Description 20-bit buffer/line driver
Datasheet 74ALVCH16827 Datasheet74ALVCH16827 Datasheet (PDF)

INTEGRATED CIRCUITS 74ALVCH16827 20-bit buffer/line driver, non-inverting (3-State) Product specification IC24 Data Handbook 1998 Jul 27 Philips Semiconductors Philips Semiconductors Product specification 20-bit buffer/line driver, non-inverting (3-State) 74ALVCH16827 FEATURES • Wide supply voltage range of 1.2V to 3.6V • Complies with JEDEC standard no. 8-1A • Wide supply voltage range of 1.2V to 3.6V • CMOS low power consumption • Direct interface with TTL levels • Universal bus transc.

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INTEGRATED CIRCUITS 74ALVCH16827 20-bit buffer/line driver, non-inverting (3-State) Product specification IC24 Data Handbook 1998 Jul 27 Philips Semiconductors Philips Semiconductors Product specification 20-bit buffer/line driver, non-inverting (3-State) 74ALVCH16827 FEATURES • Wide supply voltage range of 1.2V to 3.6V • Complies with JEDEC standard no. 8-1A • Wide supply voltage range of 1.2V to 3.6V • CMOS low power consumption • Direct interface with TTL levels • Universal bus transceiver with D-type latches and D-type flip-flops capable of operating in transparent, latched, clocked or clocked-enabled mode. DESCRIPTION The 74ALVCH16827 is a 20-bit non-inverting buffer/driver with 3-State outputs for bus oriented applications. The 74ALVCH16827 consists of two 10-bit sections with separate output enable signals. For either 10-bit buffer section, the two output enable (1OE1 and 1OE2 or 2OE1 and 2OE2) inputs must both be active. If either output enable input is high, the outputs of that 10-bit buffer section are in high impedance state. The 74ALVCH16827 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors. • MULTIBYTETM flow-through standard pin-out architecture • Low inductance multiple VCC and GND pins for minimum noise and ground bounce • Current drive ±24 mA at 3.0 V • All inputs have bus hold circuitry • Output drive capability 50Ω transmission lines @ 85°C • 3-State non-inverting outputs for bus oriented applications QUICK REFERENCE DATA GND = 0V; Tamb = 25°C; tr = tf = 2.5ns SYMBOL PARAMETER Propagation delay tPHL/tPLH CP to Qn CI Input capacitance CPD Power dissipation dissi ation capacitance ca acitance per er latch CONDITIONS VCC = 2.5V, CL = 30pF VCC = 3.3V, CL = 50pF VI = GND to VCC1 Output enabled Output disabled TYPICAL 2.0 2.0 5 20 3 UNIT ns pF pF F NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in mW): PD = CPD × VCC2 × fi + S (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; S (CL × VCC2 × fo) = sum of outputs. ORDERING INFORMATION PACKAGES 56-Pin Plastic TSSOP Type II TEMPERATURE RANGE –40°C to +85°C OUTSIDE NORTH AMERICA 74ALVCH16827 DGG NORTH AMERICA ACH16827 DGG DWG NUMBER SOT364-1 PIN DESCRIPTION PIN NUMBER 55, 54, 52, 51, 49, 48, 47, 45, 44, 43, 42, 41, 40, 38, 37, 36, 34, 33, 31, 30 2, 3, 5, 6, 8, 9, 10, 12, 13, 14, 15, 16, 17, 19, 20, 21, 23, 24, 26, 27 1, 56, 28, 29 4, 11, 18, 25, 32, 39, 46, 53 7, 22, 35, 50 SYMBOL 1A0 - 1A9 2A0 - 2A9 1Y0 - 1Y9 2Y0 - 2Y9 1OE0, 1OE1 2OE0, 2OE1 GND VCC Data inputs Data outputs Output enable inputs (active-Low) Ground (0V) Positive supply voltage FUNCTION 1998 Jul 27 2 853-2096 19785 Philips Semiconductors Product specification 20-bit buffer/line driver, non-inverting (3-State) 74ALVCH16827 PIN CONFIGURATION 1OE1 1Y0 1Y1 GND 1Y2 1Y3 VCC 1Y4 1Y5 1Y6 GND 1Y7 1Y8 1Y9 2Y0 2Y1 2Y2 GND 2Y3 2Y4 2Y5 VCC 2Y6 2Y7 GND 2Y8 2Y9 2OE1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 1OE2 1A0 1A1 GND 1A2 1A3 VCC 1A4 1A5 1A6 LOGIC SYMBOL (IEEE/IEC) 1OE1 1OE2 1 56 & EN2 & EN1 2OE1 28 2OE2 29 55 54 52 51 49 48 47 45 44 43 42 41 40 38 37 36 34 33 31 30 1A0 1A1 1A2 1A3 1A4 1A5 1 1∇ 2 3 5 6 8 9 10 12 13 14 1Y0 1Y1 1Y2 1Y3 1Y4 1Y5 1Y6 1Y7 1Y8 1Y9 2Y0 2Y1 2Y2 2Y3 2Y4 2Y5 2Y6 2Y7 2Y8 2Y9 GND 1A6 1A7 1A8 1A9 2A0 2A1 2A2 GND 2A3 2A4 2A5 VCC 2A6 2A7 GND 2A8 2A9 2OE2 1A7 1A8 1A9 2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 2A9 1 2∇ 15 16 17 19 20 21 23 24 26 27 SH00012 SH00010 LOGIC SYMBOL 55 54 52 51 49 48 47 45 44 43 FUNCTION TABLE INPUTS OUTPUTS A L H X X Y L H Z Z nOE1 L nOE2 L L H 1A0 1A1 1A2 1A3 1A4 1A5 1A6 1 56 1OE1 1OE2 1Y0 1Y1 1Y2 1Y3 1Y4 1Y5 1Y6 1A7 1A8 1A9 1Y7 1Y8 1Y9 L H 2 42 3 41 5 40 6 38 8 37 9 36 10 34 12 33 13 31 14 30 2A0 2A1 2A2 2A3 2A4 2A5 2A6 28 29 2OE1 2OE2 2Y0 2Y1 2Y2 2Y3 2Y4 2Y5 2Y6 2A7 2A8 2A9 H L X Z = = = = X H High voltage level Low voltage level Don’t care High impedance “off” state 2Y7 2Y8 2Y9 15 16 17 19 20 21 23 24 26 27 SH00011 1998 Jul 27 3 Philips Semiconductors Product specification 20-bit buffer/line driver, non-inverting (3-State) 74ALVCH16827 LOGIC DIAGRAM nA0 nA1 nA2 nA3 nA4 nA5 nA6 nA7 nA8 nA9 nOE1 nOE2 nY0 nY1 nY2 nY3 nY4 nY5 nY6 nY7 nY8 nY9 SH00013 RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER DC supply voltage 2.5V range (for max. speed performance @ 30 pF output load) VCC DC supply voltage 3.3V range (for max. speed performance @ 50 pF output load) DC Input voltage range DC output voltage range Operating free-air temperature range Input rise and fall times VCC = 2.3 to 3.0V VCC = 3.0 to 3.6V CONDITIONS MIN 2.3 3.0 0 0 –40 0 0 MAX 2.7 V 3.6 VCC VCC +85 20 10 V V °C ns/V UNIT VI VO Tamb tr, tf ABSOLUTE .


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