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INTEGRATED CIRCUITS
74F00 Quad 2-input NAND gate
Product specification IC15 Data Handbook 1990 Oct 04
Philips Semiconductors
Philips Semiconductors
Product specification
Quad 2-input NAND gate
74F00
FEATURE
• Industrial temperature range available (–40°C to +85°C)
TYPE TYPICAL PROPAGATION DELAY 3.4ns TYPICAL SUPPLY CURRENT (TOTAL) 4.4mA
PIN CONFIGURATION
D0a D0b Q0 D1a D1b Q1 GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC D3b D3a Q3 D2b D2a Q2
74F00
SF00001
ORDERING INFORMATION
ORDER CODE DESCRIPTION 14-pin plastic DIP 14-pin plastic SO COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F00N N74F00D INDUSTRIAL RANGE VCC = 5V ±10%, Tamb = –40°C to +85°C I74F00N I74F00D PKG DWG # SOT27-1 SOT108-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS Dna, Dnb Data inputs DESCRIPTION 74F (U.L.) HIGH/LOW 1.0/1.0 LOAD VALUE HIGH/LOW 20µA/0.6mA 1.0mA/20mA
Qn Data output 50/33 NOTE: One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
LOGIC DIAGRAM
D0a D0b D1a D1b D2a D2b VCC = Pin 14 GND = Pin 7 D3a D3b 1 2 4 5 9 10 12 13 11 3 Q0
FUNCTION TABLE
INPUTS Dna L L
8 Q2
OUTPUT Dnb L H L Qn H H H L
6
Q1
H
Q3
SF00002
H H NOTES: H = High voltage level L = Low voltage level
LOGIC SYMBOL
IEC/IEEE SYMBOL
1 1 2 4 5 9 10 12 13 2
&
3
4 6 D0a D0bD1a D1b D2a D2b D3a D3b 5
9 Q0 Q1 Q2 Q3 8 10
12 3 VCC = Pin 14 GND = Pin 7 6 8 11 11 13
SF00003
SF00004
October 4, 1990
2
853-0325 00623
Philips Semiconductors
Product specification
Quad 2-input NAND gate
74F00
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free air temperature range.) SYMBOL VCC VIN IIN VOUT IOUT Tamb Tstg Supply voltage Input voltage Input current Voltage applied to output in high output state Current applied to output in low output state Operating free air temperature range Commercial range Industrial range Storage temperature range PARAMETER RATING –0.5 to +7.0 –0.5 to +7.0 –30 to +5 –0.5 to VCC 40 0 to +70 –40 to +85 –65 to +150 UNIT V V mA V mA °C °C °C
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER MIN VCC VIH VIL IIk IOH IOL Tamb Supply voltage High-level input voltage Low-level input voltage Input clamp current High-level output current Low-level output current Operating free air temperature range Commercial range Industrial range 0 –40 4.5 2.0 0.8 –18 –1 20 +70 +85 LIMITS NOM 5.0 MAX 5.5 V V V mA mA mA °C °C UNIT
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL VOH VOL VIK II IIH IIL IOS ICC PARAMETER High-level output voltage TEST CONDITIONS1 MIN VCC = MIN, VIL = MAX VIH = MIN, IOH = MAX Low-level output voltage VCC = MIN, VIL = MAX VIH = MIN, IOl = MAX Input clamp voltage Input current at maximum input voltage High-level input current Low-level input current Short-circuit output current3 Supply current (total) ICCH ICCL VCC = MIN, II = IIK VCC = MAX, VI = 7.0V VCC = MAX, VI = 2.7V VCC = MAX, VI = 0.5V VCC = MAX VCC = MAX VCC = MAX VIN = GND VIN = 4.5V -60 1.9 6.8 ±10%VCC ±5%VCC ±10%VCC ±5%VCC 2.5 2.7 3.4 0.30 0.30 -0.73 0.50 0.50 -1.2 100 20 -0.6 -150 2.8 10.2 LIMITS TYP2 MAX V V V V V µA µA mA mA mA UNIT
mA NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last.
October 4, 1990
3
Philips Semiconductors
Product specification
Quad 2-input NAND gate
74F00
AC ELECTRICAL CHARACTERISTICS
LIMITS SYMBOL PARAMETER TEST CONDITION VCC = +5.0V Tamb = +25°C CL = 50pF, RL = 500Ω MIN tPLH tPHL Propagation delay Dna, Dnb to Qn Waveform 1 2.4 2.0 TYP 3.7 3.2 MAX 5.0 4.3 VCC = +5.0V ± 10% Tamb = 0°C to +70°C CL = 50pF, RL = 500Ω MIN 2.4 2.0 MAX 6.0 5.3 VCC = +5.0V ± 10% Tamb = –40°C to +85°C CL = 50pF, RL = 500Ω MIN 2.0 1.5 MAX 6.5 6.0 ns UNIT
AC WAVEFORMS
For all waveforms, VM = 1.5V.
Dna, Dnb
VM tPHL
VM tPLH
Qn
VM
VM
SF00005
Waveform 1. Propagation delay for inverting outputs
TEST CIRCUIT AND WAVEFORM
VCC NEGATIVE PULSE VIN PULSE GENERATOR RT D.U.T. VOUT 90% VM 10% tTHL (tf ) CL RL tw VM 10% tTLH (tr ) 0V 90% AMP (V)
tTLH (tr ) 90% POSITIVE PULSE VM 10% tw
tTHL (tf ) AMP (V) 90% VM 10% 0V
Test Circuit for Totem-Pole Outputs DEFINITIONS: RL = Load resistor; see AC ELECTRICAL CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC ELECTRICAL CHARACT.