NAND gate. 74F00 Datasheet

74F00 gate. Datasheet pdf. Equivalent

Part 74F00
Description Quad 2-input NAND gate
Feature INTEGRATED CIRCUITS 74F00 Quad 2-input NAND gate Product specification IC15 Data Handbook 1990 Oct .
Manufacture NXP
Datasheet
Download 74F00 Datasheet



74F00
INTEGRATED CIRCUITS
74F00
Quad 2-input NAND gate
Product specification
IC15 Data Handbook
Philips
Semiconductors
1990 Oct 04



74F00
Philips Semiconductors
Quad 2-input NAND gate
Product specification
74F00
FEATURE
Industrial temperature range available (–40°C to +85°C)
TYPE
74F00
TYPICAL
PROPAGATION
DELAY
3.4ns
TYPICAL
SUPPLY CURRENT
(TOTAL)
4.4mA
PIN CONFIGURATION
D0a 1
D0b 2
Q0 3
D1a 4
D1b 5
Q1 6
GND 7
14 VCC
13 D3b
12 D3a
11 Q3
10 D2b
9 D2a
8 Q2
SF00001
ORDERING INFORMATION
DESCRIPTION
14-pin plastic DIP
ORDER CODE
COMMERCIAL RANGE
VCC = 5V ±10%, Tamb = 0°C to +70°C
N74F00N
INDUSTRIAL RANGE
VCC = 5V ±10%, Tamb = –40°C to +85°C
I74F00N
14-pin plastic SO
N74F00D
I74F00D
PKG DWG #
SOT27-1
SOT108-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
DESCRIPTION
74F (U.L.) HIGH/LOW
Dna, Dnb
Data inputs
1.0/1.0
Qn Data output
50/33
NOTE: One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
LOAD VALUE HIGH/LOW
20µA/0.6mA
1.0mA/20mA
LOGIC DIAGRAM
D0a 1
D0b 2
D1a 4
D1b 5
VCC = Pin 14
GND = Pin 7
D2a 9
D2b 10
12
D3a
D3b 13
LOGIC SYMBOL
3
Q0
6
Q1
8
Q2
11
Q3
SF00002
FUNCTION TABLE
INPUTS
Dna Dnb
LL
LH
HL
HH
NOTES:
H = High voltage level
L = Low voltage level
IEC/IEEE SYMBOL
OUTPUT
Qn
H
H
H
L
1 2 4 5 9 10 12 13
1&
3
2
D0a D0bD1a D1bD2a D2b D3a D3b
Q0 Q1 Q2 Q3
4
6
5
9
8
10
VCC = Pin 14
GND = Pin 7
3 6 8 11
SF00003
12
13
11
SF00004
October 4, 1990
2 853-0325 00623





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