NAND gate. 74F00 Datasheet

74F00 gate. Datasheet pdf. Equivalent

74F00 Datasheet
Recommendation 74F00 Datasheet
Part 74F00
Description Quad 2-input NAND gate
Feature 74F00; INTEGRATED CIRCUITS 74F00 Quad 2-input NAND gate Product specification IC15 Data Handbook 1990 Oct .
Manufacture NXP
Datasheet
Download 74F00 Datasheet





NXP 74F00
INTEGRATED CIRCUITS
74F00
Quad 2-input NAND gate
Product specification
IC15 Data Handbook
Philips
Semiconductors
1990 Oct 04



NXP 74F00
Philips Semiconductors
Quad 2-input NAND gate
Product specification
74F00
FEATURE
Industrial temperature range available (–40°C to +85°C)
TYPE
74F00
TYPICAL
PROPAGATION
DELAY
3.4ns
TYPICAL
SUPPLY CURRENT
(TOTAL)
4.4mA
PIN CONFIGURATION
D0a 1
D0b 2
Q0 3
D1a 4
D1b 5
Q1 6
GND 7
14 VCC
13 D3b
12 D3a
11 Q3
10 D2b
9 D2a
8 Q2
SF00001
ORDERING INFORMATION
DESCRIPTION
14-pin plastic DIP
ORDER CODE
COMMERCIAL RANGE
VCC = 5V ±10%, Tamb = 0°C to +70°C
N74F00N
INDUSTRIAL RANGE
VCC = 5V ±10%, Tamb = –40°C to +85°C
I74F00N
14-pin plastic SO
N74F00D
I74F00D
PKG DWG #
SOT27-1
SOT108-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
DESCRIPTION
74F (U.L.) HIGH/LOW
Dna, Dnb
Data inputs
1.0/1.0
Qn Data output
50/33
NOTE: One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
LOAD VALUE HIGH/LOW
20µA/0.6mA
1.0mA/20mA
LOGIC DIAGRAM
D0a 1
D0b 2
D1a 4
D1b 5
VCC = Pin 14
GND = Pin 7
D2a 9
D2b 10
12
D3a
D3b 13
LOGIC SYMBOL
3
Q0
6
Q1
8
Q2
11
Q3
SF00002
FUNCTION TABLE
INPUTS
Dna Dnb
LL
LH
HL
HH
NOTES:
H = High voltage level
L = Low voltage level
IEC/IEEE SYMBOL
OUTPUT
Qn
H
H
H
L
1 2 4 5 9 10 12 13
1&
3
2
D0a D0bD1a D1bD2a D2b D3a D3b
Q0 Q1 Q2 Q3
4
6
5
9
8
10
VCC = Pin 14
GND = Pin 7
3 6 8 11
SF00003
12
13
11
SF00004
October 4, 1990
2 853-0325 00623



NXP 74F00
Philips Semiconductors
Quad 2-input NAND gate
Product specification
74F00
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free air temperature range.)
SYMBOL
PARAMETER
VCC
VIN
IIN
VOUT
IOUT
Tamb
Supply voltage
Input voltage
Input current
Voltage applied to output in high output state
Current applied to output in low output state
Operating free air temperature range
Commercial range
Industrial range
Tstg Storage temperature range
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
–0.5 to VCC
40
0 to +70
–40 to +85
–65 to +150
UNIT
V
V
mA
V
mA
°C
°C
°C
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
VCC
VIH
VIL
IIk
IOH
IOL
Tamb
Supply voltage
High-level input voltage
Low-level input voltage
Input clamp current
High-level output current
Low-level output current
Operating free air temperature range
Commercial range
Industrial range
LIMITS
MIN
NOM
MAX
4.5 5.0 5.5
2.0
0.8
–18
–1
20
0 +70
–40 +85
UNIT
V
V
V
mA
mA
mA
°C
°C
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST CONDITIONS1
LIMITS
MIN
TYP2
MAX
UNIT
VOH High-level output voltage
VCC = MIN, VIL = MAX ±10%VCC
2.5
VIH = MIN, IOH = MAX
±5%VCC
2.7
VOL Low-level output voltage
VCC = MIN, VIL = MAX ±10%VCC
VIH = MIN, IOl = MAX
±5%VCC
VIK Input clamp voltage
VCC = MIN, II = IIK
II Input current at maximum input VCC = MAX, VI = 7.0V
voltage
3.4
0.30
0.30
-0.73
0.50
0.50
-1.2
100
V
V
V
V
V
µA
IIH High-level input current
VCC = MAX, VI = 2.7V
20 µA
IIL Low-level input current
VCC = MAX, VI = 0.5V
-0.6 mA
IOS
Short-circuit output current3
VCC = MAX
-60
-150
mA
ICC
Supply current (total)
ICCH VCC = MAX
VIN = GND
1.9 2.8 mA
ICCL VCC = MAX
VIN = 4.5V
6.8 10.2 mA
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at VCC = 5V, Tamb = 25°C.
3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, IOS tests should be performed last.
October 4, 1990
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