Undershoot/Overshoot Clamp. 74F1071 Datasheet

74F1071 Clamp. Datasheet pdf. Equivalent


Fairchild Semiconductor 74F1071
October 1994
Revised August 1999
74F1071
18-Bit Undershoot/Overshoot Clamp
and ESD Protection Device
General Description
The 74F1071 is an 18-bit undershoot/overshoot clamp
which is designed to limit bus voltages and also to protect
more sensitive devices from electrical overstress due to
electrostatic discharge (ESD). The inputs of the device
aggressively clamp voltage excursions nominally at 0.5V
below and 7V above ground.
Features
s 18-bit array structure in 20-pin package
s FAST® Bipolar voltage clamping action
s Dual center pin grounds for min inductance
s Robust design for ESD protection
s Low input capacitance
s Optimum voltage clamping for 5V CMOS/TTL
applications
Ordering Code:
Order Number Package Number
Package Description
74F1071SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F1071MSA
MSA20
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74F1071MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Note: Simplified Component Representation
FAST® is a registered trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation DS011685
www.fairchildsemi.com


74F1071 Datasheet
Recommendation 74F1071 Datasheet
Part 74F1071
Description 18-Bit Undershoot/Overshoot Clamp
Feature 74F1071; 74F1071 18-Bit Undershoot/Overshoot Clamp October 1994 Revised August 1999 74F1071 18-Bit Undersho.
Manufacture Fairchild Semiconductor
Datasheet
Download 74F1071 Datasheet




Fairchild Semiconductor 74F1071
Absolute Maximum Ratings(Note 1)
Storage Temperature
65°C to +150°C
Ambient Temperature under Bias
65°C to +125°C
Junction Temperature under Bias
65°C to +150°C
Input Voltage (Note 2)
0.5V to +6V
Input Current (Note 2)
200 mA to +50 mA
ESD (Note 3)
Human Body Model
(MIL-STD-883D method 3015.7)
±10 kV
IEC 801-2
±6 kV
Machine Model (EIAJIC-121-1981)
±2 kV
DC Latchup Source Current
(JEDEC Method 17)
±500 mA
Package Power Dissipation @+70°C
SOIC Package
800 mW
Recommended Operating
Conditions
Free Air Ambient Temperature
Reverse Bias Voltage
Thermal Resistance (θJA in Free Air)
SOIC Package
SSOP Package
0°C to +70°C
0V to 5.25 VDC
100°C/W
110°C/W
Note 1: Absolute maximum ratings are DC values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: Voltage ratings may be exceeded if current ratings and junction
temperature and power consumption ratings are not exceeded.
Note 3: ESD Rating for Direct contact discharge using ESD Simulation
Tester. Higher rating may be realized in the actual application.
DC Electrical Characteristics
Symbol
Parameter
IIH Input HIGH Current
VZ Reverse Voltage
VF Forward Voltage
ICT Adjacent Input Crosstalk
CIN Input Capacitance
(small signal @ 1 MHz)
Min
6.6
0.3
0.5
TA = +25°C
Typ
1.5
3
6.9
7.1
0.6
1.1
25
13
Max
10
20
7.2
7.5
0.9
1.5
3
TA = 0°C to +70°C
Min Max
50
100
5.9 7.7
8.0
0.3
0.9
0.5
1.5
Units
Conditions
µA VIN = 5.25V; Untested Input @ GND
VIN = 5.5V; Untested Input @ GND
V IZ = 1 mA; Untested Inputs @ GND
IZ = 50 mA; Untested Inputs @ GND
V IF = −18 mA; Untested Inputs @ 5V
IF = −200 mA; Untested Inputs @ 5V
%
pF VBIAS = 0 VDC
VBIAS = 5 VDC
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Fairchild Semiconductor 74F1071
DC Electrical Characteristics
Typical Forward and Reverse V/I
Characteristics
Typical Reverse Conduction
Characteristics
Typical Forward Conduction
Characteristics
ESD Network
Human Body Model
IEC 801-2
CZ
100 pF
150 pF
RZ
1500
330
Simulated ESD Voltage Clamping Test Circuit
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