Edge-Triggered Flip-Flop. 74F109 Datasheet

74F109 Flip-Flop. Datasheet pdf. Equivalent


Fairchild Semiconductor 74F109
April 1988
Revised November 1999
74F109
Dual JK Positive Edge-Triggered Flip-Flop
General Description
The F109 consists of two high-speed, completely indepen-
dent transition clocked JK flip-flops. The clocking operation
is independent of rise and fall times of the clock waveform.
The JK design allows operation as a D-type flip-flop (refer
to F74 data sheet) by connecting the J and K inputs.
Asynchronous Inputs:
LOW input to SD sets Q to HIGH level
LOW input to CD sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CD and SD makes
both Q and Q HIGH
Ordering Code:
Order Number Package Number
Package Description
74F109SC
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150Narrow Body
74F109SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE 11, 5.3mm Wide
74F109PC
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation DS009471
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74F109 Datasheet
Recommendation 74F109 Datasheet
Part 74F109
Description Dual JK Positive Edge-Triggered Flip-Flop
Feature 74F109; 74F109 Dual JK Positive Edge-Triggered Flip-Flop April 1988 Revised November 1999 74F109 Dual JK P.
Manufacture Fairchild Semiconductor
Datasheet
Download 74F109 Datasheet




Fairchild Semiconductor 74F109
Truth Table
Inputs
Outputs
SD CD CP
J
K
Q
Q
LHXXXHL
HLXXXLH
L L XXXHH
H H
I I LH
H H
hI
Toggle
H H
I h QQ
H H
h hHL
HHL XXQ
H (h) = HIGH Voltage Level
L (l) = LOW Voltage Level
= LOW-to-HIGH Transition
X = Immaterial
Q0 (Q0) = Before LOW-to-HIGH Transition of Clock
Lower case letters indicate the state of the referenced output one setup time prior to the LOW-to-HIGH clock transition.
Q
Unit Loading/Fan Out
Pin Names
Description
U.L.
Input IIH/IIL
HIGH/LOW Output IOH/IOL
J1, J2, K1, K2 Data Inputs
CP1, CP2
Clock Pulse Inputs (Active Rising Edge)
CD1, CD2
Direct Clear Inputs (Active LOW)
SD1, SD2
Direct Set Inputs (Active LOW)
Q1, Q2, Q1, Q2 Outputs
1.0/1.0
1.0/1.0
1.0/3.0
1.0/3.0
50/33.3
20 µA/0.6 mA
20 µA/0.6 mA
20 µA/1.8 mA
20 µA/1.8 mA
1 mA/20 mA
Block Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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Fairchild Semiconductor 74F109
Absolute Maximum Ratings(Note 1)
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
VCC Pin Potential to
Ground Pin
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Output
in HIGH State (with Vcc = 0V)
Standard Output
3-STATE Output
Current Applied to Output
in LOW State (Max)
65°C to +150°C
55°C to +125°C
55°C to +175°C
0.5V to +7.0V
0.5V to +7.0V
30 mA to +5.0 mA
0.5V to VCC
0.5V to +5.5V
twice the rated IOL (mA)
Recommended Operating
Conditions
Free Air Ambient Temperature
Supply Voltage
0°C to +70°C
+4.5V to +5.5V
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
Parameter
VIH
VIL
VCD
VOH
VOL
IIH
IBVI
ICEX
VID
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Current
10% VCC
5% VCC
10% VCC
Input HIGH Current Breakdown Test
Output HIGH Leakage Current
Input Leakage Test
IOD Output Leakage
Circuit Current
IIL Input LOW Current
IOS Output Short-Circuit Current
ICC Power Supply Current
Min
Typ
Max
Units
VCC
Conditions
2.0
2.5
2.7
4.75
V Recognized as a HIGH Signal
0.8 V
Recognized as a LOW Signal
1.2 V Min IIN = −18 mA
IOH = −1 mA
V Min
IOH = −1 mA
0.5 V Min IOL = 20 mA
5.0 µA Max VIN = 2.7V
7.0 µA Max VIN = 7.0V
50 µA Max VOUT = VCC
IID = 1.9 µA
V 0.0
All Other Pins Grounded
3.75
µA
VIOD = 150 mV
0.0
All Other Pins Grounded
0.6 mA Max VIN = 0.5V (Jn, Kn)
1.8 mA Max VIN = 0.5V (CDn, SDn)
60
150
mA
Max VOUT = 0V
11.7 17.0 mA Max CP = 0V
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