74F125

74F125 Quad Buffer (3-STATE) April 1988 Revised July 1999 74F125 Quad Buffer (3-STATE) Features s High impedance base inputs for reduced loading Ordering Code: Order Number 74F125SC 74F125SJ 74F125PC Package Number M14A M14D N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol IEEE/IEC Connection Diagram Unit Loading/Fan Out U.L. Pin Names An, Bn On Description HIGH/LOW Inputs Outputs 1.0/0.033 600/106.6 (80) Input IIH/I IL Output I OH/IOL 20 µA/ −20 µA −12 mA/64 mA (48 mA) Function Table Inputs An L L H H = HIGH Voltage Level L = LOW Voltage Level Z = High Impedance X = Immaterial Output Bn L H X O L H Z © 1999 Fairchild Semiconductor Corporation DS009475 www.fairchildsemi.com 74F125 Absolute Maximum Ratings(Note 1) Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output 3-STATE Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA) −0.5V to VCC −0.5V to +5.5V −65 °C to +150°C −55 °C to +125°C −55 °C to +150°C −0.5V to +7.0V −0.5V to +7.0V −30 mA to +5.0 mA Recommended Op...