DatasheetsPDF.com

74F169 Dataheets PDF



Part Number 74F169
Manufacturers NXP
Logo NXP
Description 4-bit up/down binary synchronous counter
Datasheet 74F169 Datasheet74F169 Datasheet (PDF)

INTEGRATED CIRCUITS 74F168*, 74F169 4-bit up/down binary synchronous counter * Discontinued part. Please see the Discontinued Product List in Section 1, page 21. Product specification IC15 Data Handbook 1996 Jan 05 Philips Semiconductors Philips Semiconductors Product specification 4-bit up/down binary synchronous counter 74F169 FEATURES • Synchronous counting and loading • Up/Down counting • Modulo 16 binary counter • Two Count Enable inputs for n-bit cascading • Positive edge-trigger.

  74F169   74F169



Document
INTEGRATED CIRCUITS 74F168*, 74F169 4-bit up/down binary synchronous counter * Discontinued part. Please see the Discontinued Product List in Section 1, page 21. Product specification IC15 Data Handbook 1996 Jan 05 Philips Semiconductors Philips Semiconductors Product specification 4-bit up/down binary synchronous counter 74F169 FEATURES • Synchronous counting and loading • Up/Down counting • Modulo 16 binary counter • Two Count Enable inputs for n-bit cascading • Positive edge-triggered clock • Built-in carry look-ahead capability • Presettable for programmable operation DESCRIPTION The 74F169 is a 4-bit synchronous, presettable Modulo 16 up/down counter featuring an internal carry look-ahead for applications in high-speed counting designs. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when instructed by the Count Enable inputs and internal gating. This mode of operation eliminates the output spikes which are normally associated with asynchronous (ripple clock) counters. A buffered clock input triggers the flip-flops on the Low-to-High transition of the clock. The counter is fully programmable; that is, the outputs may be preset to either level. Presetting is synchronous with the clock and takes place regardless of the levels of the Count Enable inputs. A Low level on the Parallel Enable (PE) input disables the counter and causes the data at the Dn input to be loaded into the counter on the next Low-to-High transition of the clock. The direction of counting is controlled by the Up/Down (U/D) input; a High will cause the count to increase, a Low will cause the count to decrease. The carry look-ahead circuitry provides for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are two Count Enable inputs (CET, CEP) and a Terminal Count (TC) output. Both Count Enable inputs must be Low to count. The CET input is fed forward to enable the TC output. The TC output thus enabled will produce a Low output pulse with a duration approximately equal to the High level portion of the Q0 output. The Low level TC pulse is used to enable successive cascaded stages. PIN CONFIGURATION U/D CP D0 D1 D2 D3 CEP GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC TC Q0 Q1 Q2 Q3 CET PE SF00766 TYPE 74F169 TYPICAL fMAX 115MHz TYPICAL SUPPLY CURRENT (TOTAL) 35mA ORDERING INFORMATION ORDER CODE DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F169N N74F169D PKG DWG # SOT38-4 SOT109-1 16-pin plastic DIP 16-pin plastic SO INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS D0 - D3 CEP CET CP PE U/D Q 0 - Q3 Parallel data inputs Count Enable parallel input (active Low) Count Enable Trickle input (active Low) Clock input (active rising edge) Parallel Enable input (active Low) Up/Down count control input Flip-flop outputs DESCRIPTION 74F(U.L.) HIGH/LOW 1.0/1.0 1.0/1.0 1.0/2.0 1.0/1.0 1.0/1.0 1.0/1.0 50/33 LOAD VALUE.


74F166 74F169 74F169


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site.
(Privacy Policy & Contact)