74F173

INTEGRATED CIRCUITS 74F173 Quad D-type flip-flop (3-State) Product specification IC15 Data Handbook 1990 Aug 31 Philips Semiconductors Philips Semiconductors Product specification Quad D-type flip–flop (3-State) 74F173 FEATURES Edge–triggered D–type register Gated clock enable for hold ”do nothing” mode 3–state output buffers Gated output enable control Speed upgrade of N8T10 and current sink upgrade Controlled output edges to minimize ground bounces 48mA sinking capability DESCRIPTION The 74F173 is a high speed 4–bit parallel load register with clock enable control, 3–state buffered outputs, and master reset (MR). When the two clock enable (E0 and E1) inputs are low, the data on the D inputs is loaded into the register simultaneously with low–to–high clock (CP) transition. When one or both enable inputs are high one setup time before the low–to–high clock transition, the register retains the previous data. TYPE 74F173 TYPICAL fmax 125MHz Data inputs and clock enable inputs are fully edge–triggered and must be stable only one setup time before the low–to–high clock transition. The master reset (MR) is an active–high asynchronous input. When the MR is high, all four flip–flops are reset (cleared) independently of any other input condition. The 3–state output buffers are controlled by a 2–input NOR gate. When both output enable (OE0 and OE1) inputs are low, the data in the register is presented at the Q output. When one or both OE inputs are high, the out...