74F174

54F 74F174 Hex D Flip-Flop with Master Reset November 1994 54F 74F174 Hex D Flip-Flop with Master Reset General Description The ’F174 is a high-speed hex D flip-flop The device is used primarily as a 6-bit edge-triggered storage register The information on the D inputs is transferred to storage during the LOW-to-HIGH clock transition The device has a Master Reset to simultaneously clear all flip-flops Features Y Y Y Y Edge-triggered D-type inputs Buffered positive edge-triggered clock Asynchronous common reset Guaranteed 4000V minimum ESD protection Commercial 74F174PC Military Package Number N16E Package Description 16-Lead (0 300 Wide) Molded Dual-In-Line 16-Lead Ceramic Dual-In-Line 16-Lead (0 150 Wide) Molded Small Outline JEDEC 16-Lead (0 300 Wide) Molded Small Outline EIAJ 16-Lead Cerpack 20-Lead Ceramic Leadless Chip Carrier Type C 54F174DM (Note 2) 74F174SC (Note 1) 74F174SJ (Note 1) 54F174FM (Note 2) 54F174LM (Note 2) J16A M16A M16D W16A E20A Note 1 Devices also available in 13 reel Use Suffix e SCX and SJX Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB Logic Symbols Connection Diagrams Pin Assignment for DIP SOIC and Flatpak Pin Assignment for LCC TL F 9489–3 TL F 9489 – 1 TL F 9489 – 2 IEEE IEC TL F 9489–5 TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TL F 9489 RRD-B30M75 Printed in U S A Unit Loading Fan Out 54F 74F Pin N...