74F1763

INTEGRATED CIRCUITS 74F1763 Intelligent DRAM controller (IDC) Product specification Supersedes data of 1989 Nov 17 IC15 Data Handbook 1999 Jan 08 Philips Semiconductors Philips Semiconductors Product specification Intelligent DRAM controller (IDC) 74F1763 FEATURES DRAM signal timing generator Automatic refresh circuitry Selectable row address hold and RAS precharge times Facilitates page mode accesses Controls 1 MBit DRAMs Intelligent burst-mode refresh after page-mode access cycles PRODUCT DESCRIPTION The Philips Semiconductors Intelligent Dynamic RAM Controller is a 1 MBit, single-port version of the 74F1764 Dual Port Dynamic RAM Controller. It contains automatic signal timing, address multiplexing and refresh control required for interfacing with dynamic RAMs. Additional features have been added to this device to take advantage of technological advances in Dynamic RAMs. A Page-Mode access pin allows the user to assert RAS for the entire access cycle rather than the pre-defined four-clock-cycle pulse width used for normal random access cycles. In addition, the user has the ability to select the RAS precharge time and Row-Address Hold time to fit the particular DRAMs being used. DTACK has been modified from previous family parts to become a negative true, tri-stated output. The options for latched or unlatched address are contained on a single device by the addition of an Address Latch Enable (ALE) input. Finally, a burst refresh monitor has been added t...