IDT54FCT162511AT

Integrated Device Technology, Inc. FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY IDT54/74FCT162511AT/CT FEATURES: 0.5 MICRON CMOS Technology Typical tsk(o) (Output Skew) < 250ps, clocked mode Low input and output leakage ≤1µA (max) ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) Packages include 25 mil pitch SSOP, 19.6 mil pitch TSSOP, 15.7 mil pitch TVSOP and 25 mil pitch Cerpack Extended commercial range of –40°C to +85°C VCC = 5V ±10% Balanced Output Drivers: ±24mA (commercial) ±16mA (military) Series current limiting resistors Generate/Check, Check/Check modes Open drain parity error allows wire-OR DESCRIPTION: The FCT162511AT/CT 16-bit registered/latched transceiver with parity is built using advanced dual metal CMOS technology. This high-speed, low-power transceiver combines D- type latches and D-type flip-flops to allow data flow in transparent, latched or clocked modes. The device has a parity generator/cheker in the A-to-B direction and a parity checker in the B-to-A direction. Error checking is done at the byte level with separate parity bits for each byte. Separate error flags exits for each direction with a single error flag indicating an error for either byte in the A-to-B direction and a second error flag indicating an error for either byte in the B-to-A direction. The parity error flags are open drain outputs which can be tied together and/or tied with flags from other devices to f...