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IDT54FCT16270TE Dataheets PDF



Part Number IDT54FCT16270TE
Manufacturers Integrated Device Technology
Logo Integrated Device Technology
Description FAST CMOS 18-BIT R/W BUFFER
Datasheet IDT54FCT16270TE DatasheetIDT54FCT16270TE Datasheet (PDF)

FAST CMOS 18-BIT R/W BUFFER Integrated Device Technology, Inc. IDT54/74FCT162701T/AT FEATURES: • • • • • • • • • • • • • • 0.5 MICRON CMOS Technology Typical tSK(o) (Output Skew) < 250ps Low input and output leakage ≤1µ A (max.) ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) Packages include 25 mil pitch SSOP, 19.6 mil pitch TSSOP, 15.7 mil pitch TVSOP and 25 mil pitch Cerpack Extended commercial range of -40°C to +85°C Balanced Output Drivers: ±24mA (c.

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FAST CMOS 18-BIT R/W BUFFER Integrated Device Technology, Inc. IDT54/74FCT162701T/AT FEATURES: • • • • • • • • • • • • • • 0.5 MICRON CMOS Technology Typical tSK(o) (Output Skew) < 250ps Low input and output leakage ≤1µ A (max.) ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) Packages include 25 mil pitch SSOP, 19.6 mil pitch TSSOP, 15.7 mil pitch TVSOP and 25 mil pitch Cerpack Extended commercial range of -40°C to +85°C Balanced Output Drivers: ±24mA (commercial), ±16mA (military) Reduced system switching noise Typical VOLP (Output Ground Bounce) < 0.6V at VCC = 5V, TA = 25°C Ideal for new generation x86 write-back cache solutions Suitable for modular x86 architectures Four deep write FIFO Latch in read path Synchronous FIFO reset DESCRIPTION: The FCT162701T/AT is an 18-bit Read/Write buffer with a four deep FIFO and a read-back latch. It can be used as a read/write buffer between a CPU and memory or to interface a high-speed bus and a slow peripheral. The Ato-B (write) path has a four deep FIFO for pipelined operations. The FIFO can be reset and a FIFO full condition is indicated by the full flag (FF). The B-to-A (read) path has a latch. A HIGH on LE, allows data to flow transparently from B-to-A. A LOW on LE allows the data to be latched on the falling edge of LE. The FCT162701T/AT has a balanced output drive with series termination. This provides low ground bounce, minimal undershoot and controlled output edge rates. FUNCTIONAL BLOCK DIAGRAM A1-18 18 OEBA RESET CLK WCE RCE FF FIFO (4 deep) LATCH LE OEAB 18 2915 drw 01 B1-18 The IDT logo is a registered trademark of Integrated Device Techology, Inc. MILITARY AND COMMERCIAL TEMPERATURE RANGES ©1996 Integrated Device Technology, Inc. AUGUST 1996 DSC-2915/3 5.15 1 IDT54/74FCT162701T/AT FAST CMOS 18-BIT R/W BUFFER MILITARY AND COMMERCIAL TEMPERATURE RANGES PIN CONFIGURATIONS OEAB WCE A1 GND A2 A3 VCC A4 A5 A6 GND A7 A8 A9 A10 A11 A12 GND A13 A14 A15 VCC A16 A17 GND A18 OEBA LE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 SO56-1 43 SO56-2 SO56-3 42 41 40 39 38 37 36 35 34 33 32 31 30 29 RCE CLK B1 GND B2 B3 VCC B4 B5 B6 GND B7 B8 B9 B10 B11 B12 GND B13 B14 B15 VCC B16 B17 GND B18 FF RESET OEAB WCE A1 GND A2 A3 VCC A4 A5 A6 GND A7 A8 A9 A10 A11 A12 GND A13 A14 A15 VCC A16 A17 GND A18 OEBA LE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 CERPACK TOP VIEW E56-1 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 RCE CLK B1 GND B2 B3 VCC B4 B5 B6 GND B7 B8 B9 B10 B11 B12 GND B13 B14 B15 VCC B16 B17 GND B18 FF RESET SSOP/ TSSOP/TVSOP TOP VIEW 2915 drw 02 2915 drw 03 5.15 2 IDT54/74FCT162701T/AT FAST CMOS 18-BIT R/W BUFFER MILITARY AND COMMERCIAL TEMPERATURE RANGES PIN DESCRIPTION Pin Names A1-18 B1-18 CLK I/O I/O I/O I 18 bit I/O port. 18 bit I/O port. Clock for write path FIFO. Clocks data into FIFO whe.


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