74AC10

74AC10 TRIPLE 3-INPUT NAND GATE PRELIMINARY DATA s s s s s wiring C2MOS technology. It is ideal for low power applications mantaining high speed s operation similar to equivalent Bipolar Schottky TTL. s The internal circuit is composed of 3 stages including buffer output, which enables high noise s immunity and stable output. All inputs and outputs are equipped with DESCRIPTION protection circuits against static discharge, giving The AC10 is an advanced high-speed CMOS www.DataSheet4U.com TRIPLE 3-INPUT NAND GATE fabricated with them 2KV ESD immunity and transient excess sub-micron silicon gate and double-layer metal voltage. s HIGH SPEED: tPD = 4 ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA = 25 oC HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) 50Ω TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 10 IMPROVED LATCH-UP IMMUNITY B M (Plastic Package) (Micro Package) ORDER CODES : 74AC10B 74AC10M PIN CONNECTION AND IEC LOGIC SYMBOLS May 1997 1/7 74AC10 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1, 3, 9 2, 4, 10 13, 5, 11 12, 6, 8 7 14 SYMBOL 1A to 3A 1B to 3B 1C to 3C 1Y to 3Y GND VCC NAME AND F UNCTIO N Data Inputs Data Inputs Data Inputs Data Outputs Ground (0V) Positive Supply Voltage TRUTH TABLE A L X X H B X L X H C X X L H Y H H H L ABSOLUTE MAXIM...