61LV25616AL Datasheet: 256K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY





61LV25616AL 256K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY Datasheet

Part Number 61LV25616AL
Description 256K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY
Manufacture Integrated Silicon Solution Inc
Total Page 12 Pages
PDF Download Download 61LV25616AL Datasheet PDF

Features: IS61LV25616AL 256K x 16 HIGH SPEED ASYNC HRONOUS CMOS STATIC RAM WITH 3.3V SUPPL Y FEATURES • High-speed access time: — 10, 12 ns • CMOS low power operat ion • Low stand-by power: — Less th an 5 mA (typ.) CMOS stand-by • TTL co mpatible interface levels • Single 3. 3V power supply • Fully static operat ion: no clock or refresh required • T hree state outputs • Data control for upper and lower bytes • Industrial t emperature available ISSI FEBRUARY 200 3 ® DESCRIPTION The ISSI IS61LV25616 AL is a high-speed, 4,194,304-bit stati c RAM organized as 262,144 words by 16 bits. It is fabricated using ISSI's hig h-performance CMOS technology. This hig hly reliable process coupled with innov ative circuit design techniques, yields high-performance and low power consump tion devices. When CE is HIGH (deselect ed), the device assumes a standby mode at which the power dissipation can be r educed down with CMOS input levels. Eas y memory expansion is provided by using Chip Enable and Output Enable inputs, CE and O.

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IS61LV25616AL
256K x 16 HIGH SPEED ASYNCHRONOUS
CMOS STATIC RAM WITH 3.3V SUPPLY
ISSI®
FEBRUARY 2003
FEATURES
• High-speed access time:
— 10, 12 ns
• CMOS low power operation
• Low stand-by power:
— Less than 5 mA (typ.) CMOS stand-by
• TTL compatible interface levels
• Single 3.3V power supply
• Fully static operation: no clock or refresh
required
• Three state outputs
• Data control for upper and lower bytes
• Industrial temperature available
DESCRIPTION
The ISSI IS61LV25616AL is a high-speed, 4,194,304-bit
static RAM organized as 262,144 words by 16 bits. It is
fabricated using ISSI's high-performance CMOS technol-
ogy. This highly reliable process coupled with innovative
circuit design techniques, yields high-performance and low
power consumption devices.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs, CE and OE. The active LOW
Write Enable (WE) controls both writing and reading of the
memory. A data byte allows Upper Byte (UB) and Lower
Byte (LB) access.
The IS61LV25616AL is packaged in the JEDEC standard
44-pin 400-mil SOJ, 44-pin TSOP Type II, 44-pin LQFP and
48-pin Mini BGA (8mm x 10mm).
FUNCTIONAL BLOCK DIAGRAM
A0-A17
DECODER
256K x 16
MEMORY ARRAY
VDD
GND
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
I/O
DATA
CIRCUIT
COLUMN I/O
CE
OE CONTROL
WE CIRCUIT
UB
LB
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
02/21/03
1

                    
              






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