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61SP6464 Dataheets PDF



Part Number 61SP6464
Manufacturers Integrated Silicon Solution Inc
Logo Integrated Silicon Solution  Inc
Description 64K x 64 SYNCHRONOUS PIPELINE STATIC RAM
Datasheet 61SP6464 Datasheet61SP6464 Datasheet (PDF)

IS61SP6464 64K x 64 SYNCHRONOUS PIPELINE STATIC RAM FEATURES • Fast access time: – 117, 100 MHz • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Pentium™ or linear burst sequence control using MODE input • Five chip enables for simple depth expansion and address pipelining • Common data inputs and data outputs • Power-down control by ZZ input • JEDEC 128-Pin TQFP 14mm x 20mm package • Single +3.3V power .

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IS61SP6464 64K x 64 SYNCHRONOUS PIPELINE STATIC RAM FEATURES • Fast access time: – 117, 100 MHz • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Pentium™ or linear burst sequence control using MODE input • Five chip enables for simple depth expansion and address pipelining • Common data inputs and data outputs • Power-down control by ZZ input • JEDEC 128-Pin TQFP 14mm x 20mm package • Single +3.3V power supply • Control pins mode upon power-up: – MODE in interleave burst mode – ZZ in normal operation mode These control pins can be connected to GNDQ or VDDQ to alter their power-up state ISSI JANUARY 2004 ® DESCRIPTION The ISSI IS61SP6464 is a high-speed, low-power synchronous static RAM designed to provide a burstable, high-performance, secondary cache for the i486™, Pentium™, 680X0™, and PowerPC™ microprocessors. It is organized as 65,536 words by 64 bits, fabricated with ISSI's advanced CMOS technology. The device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be from one to eight bytes wide as controlled by the write control inputs. Separate byte enables allow individual bytes to be written. BW1 controls I/O1-I/O8, BW2 controls I/O9-I/O16, BW3 controls I/ O17-I/O24, BW4 controls I/O25-I/O32, BW5 controls I/O33-I/O40, BW6 controls I/O41-I/O48, BW7 controls I/O49-I/ O56, BW8 controls I/O57-I/O64, conditioned by BWE being LOW. A LOW on GW input would cause all bytes to be written. Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally by the IS61SP6464 and controlled by the ADV (burst address advance) input pin. Asynchronous signals include output enable (OE), sleep mode input (ZZ), and burst mode input (MODE). A HIGH input on the ZZ pin puts the SRAM in the power-down state. When ZZ is pulled LOW (or no connect), the SRAM normally operates after the wake-up period. A LOW input, i.e., GNDQ, on MODE pin selects LINEAR Burst. A VDDQ (or no connect) on MODE pin selects INTERLEAVED Burst. Copyright © 2004 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. C 01/14/04 1 IS61SP6464 BLOCK DIAGRAM ISSI MODE Q0 A0' ® CLK CLK A0 BINARY COUNTER ADV ADSC ADSP CE CLR Q1 A1' A1 64K x 64 MEMORY ARRAY 14 16 A15-A0 16 D Q ADDRESS REGISTER CE CLK 64 64 GW BWE BW8 D Q DQ57-DQ64 BYTE WRITE REGISTERS CLK D BW1 Q DQ8-DQ1 BYTE WRITE REGISTERS CLK CE CE2 CE2 CE3 CE3 D Q 8 ENABLE REGISTER CE CLK INPUT REGISTERS CLK OUTPUT REGISTERS CLK OE 64 DATA[64:1] D Q ENABLE DELAY REGISTER CLK OE 2 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. C 01/14/04 IS61SP6464 PIN CONFIGURATION 128-Pin TQFP/PQFP VDDQ CE3 CE2 CE3 CE2 GND VDD CE BW8 BW7 BW6 BW5 OE CLK BWE GW BW4 BW3 GND VDD BW2 BW1 ADSC ADSP ADV GNDQ ISSI ® 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 GNDQ I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 I/O40 I/O41 I/O42 I/O43 VDDQ GNDQ I/O44 I/O45 I/O46 I/O47 I/O48 I/O49 I/O50 I/O51 I/O52 I/O53 VDDQ GNDQ I/O54 I/O55 I/O56 I/O57 I/O58 I/O59 I/O60 I/O61 I/O62 I/O63 I/O64 VDDQ PIN DESCRIPTIONS A0-A15 CLK ADSP ADSC ADV BW1-BW8 BWE GW CE, CE2, CE2, CE3, CE3 OE Address Inputs Clock Processor Address Status Controller Address Status Burst Address Advance Synchronous Byte Write Enable Byte Write Enable Global Write Enable Synchronous Chip Enable Output Enable NC GNDQ I/O1-I/O64 ZZ MODE VDD GND VDDQ Data Input/Output Sleep Mode Burst Sequence Mode +3.3V Power Supply Ground Isolated Output Buffer Supply: +3.3V No Connect Isolated Output Buffer Ground Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. C 01/14/04 GNDQ NC MODE A15 A14 A13 VDD GND A12 A11 A10 A9 A8 NC A7 A6 A5 A4 A3 VDD GND A2 A1 A0 ZZ VDDQ 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 VDDQ I/O32 I/O31 I/O30 I/O29 I/O28 I/O27 I/O26 I/O25 I/O24 I/O23 I/O22 GNDQ VDDQ I/O21 I/O20 I.


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