62LV256 Datasheet PDF | Integrated Silicon Solution Inc





(PDF) 62LV256 Datasheet PDF

Part Number 62LV256
Description 32K x 8 LOW VOLTAGE STATIC RAM
Manufacture Integrated Silicon Solution Inc
Total Page 9 Pages
PDF Download Download 62LV256 Datasheet PDF

Features: IS62LV256 32K x 8 LOW VOLTAGE STATIC RAM ISSI DESCRIPTION ® DECEMBER 2002 F EATURES • Access time: 45, 70 ns • Low active power: 70 mW • Low standby power — 45 µW CMOS standby • Full y static operation: no clock or refresh required • TTL compatible inputs and outputs • Single 3.3V power supply The ISSI IS62LV256 is a very high-speed , low power, 32,768-word by 8-bit stati c RAM. It is fabricated using ISSI's hi gh-performance CMOS double-metal techno logy. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation is reduced to 10 µW (typical) with CMOS input levels. Easy memory expansion is provided by us ing an active LOW Chip Enable (CE) inpu t and an active LOW Output Enable (OE) input. The active LOW Write Enable (WE) controls both writing and reading of t he memory. The IS62LV256 is pin compati ble with other 32K x 8 SRAMs in 300-mil SOJ, 330-mil plastic SOP, and TSOP (Ty pe I Normal and Reverse Bent) packages. FUNCTIONAL BLOCK DIAGRAM A0-A14 DECOD.

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62LV256 datasheet
IS62LV256
ISSI®
32K x 8 LOW VOLTAGE STATIC RAM
DECEMBER 2002
FEATURES
• Access time: 45, 70 ns
• Low active power: 70 mW
• Low standby power
— 45 µW CMOS standby
• Fully static operation: no clock or refresh
required
• TTL compatible inputs and outputs
• Single 3.3V power supply
DESCRIPTION
The ISSI IS62LV256 is a very high-speed, low power,
32,768-word by 8-bit static RAM. It is fabricated using ISSI's
high-performance CMOS double-metal technology.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation is reduced to
10 µW (typical) with CMOS input levels.
Easy memory expansion is provided by using an active LOW
Chip Enable (CE) input and an active LOW Output Enable
(OE) input. The active LOW Write Enable (WE) controls both
writing and reading of the memory.
The IS62LV256 is pin compatible with other 32K x 8 SRAMs
in 300-mil SOJ, 330-mil plastic SOP, and TSOP (Type I Normal
and Reverse Bent) packages.
FUNCTIONAL BLOCK DIAGRAM
A0-A14
VCC
GND
I/O0-I/O7
DECODER
I/O
DATA
CIRCUIT
256 X 1024
MEMORY ARRAY
COLUMN I/O
CE
CONTROL
OE CIRCUIT
WE
Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. K
12/11/02
1

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