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7013 Dataheets PDF



Part Number 7013
Manufacturers Analog Devices
Logo Analog Devices
Description CMOS TIA IS-54 Baseband Receive Port
Datasheet 7013 Datasheet7013 Datasheet (PDF)

a FEATURES Single +5 V Supply Receive Channel Differential or Single-Ended Analog Inputs Auxiliary Set of Analog I & Q Inputs Two Sigma-Delta A/D Converters Choice of Two Digital FIR Filters Root-Raised-Cosine Rx Filters, α = 0.35 Brick Wall FIR Rx Filters On-Chip or User Rx Offset Calibration ADC Sampling Vernier Three Auxiliary DACs On-Chip Voltage Reference Low Active Power Dissipation, Typical 45 mW Low Sleep Mode Power Dissipation, <50 µ W 28-Pin SSOP APPLICATIONS American TIA Digital Cellu.

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a FEATURES Single +5 V Supply Receive Channel Differential or Single-Ended Analog Inputs Auxiliary Set of Analog I & Q Inputs Two Sigma-Delta A/D Converters Choice of Two Digital FIR Filters Root-Raised-Cosine Rx Filters, α = 0.35 Brick Wall FIR Rx Filters On-Chip or User Rx Offset Calibration ADC Sampling Vernier Three Auxiliary DACs On-Chip Voltage Reference Low Active Power Dissipation, Typical 45 mW Low Sleep Mode Power Dissipation, <50 µ W 28-Pin SSOP APPLICATIONS American TIA Digital Cellular Telephony American Analog Cellular Telephony Digital Baseband Receivers GENERAL DESCRIPTION The AD7013 is a complete low power, CMOS, TIA IS-54 baseband receive port with single +5 V power supply. The part is CMOS TIA IS-54 Baseband Receive Port AD7013 designed to perform the baseband conversion of I and Q waveforms in accordance with the American (TIA IS-54) Digital Cellular Telephone system. The receive path consists of two high performance sigma-delta ADCs, each followed by a FIR digital filter. A primary and auxiliary set of IQ differential analog inputs are provided, where either can be selected as inputs to the sigma-delta ADCs. Also, a choice of two frequency responses are available for the receive FIR filters; a Root-Raised-Cosine filter for digital mode or a brick wall response for analog mode. Differential analog inputs are provided for both I and Q channels. On-chip calibration logic is also provided to remove either on-chip offsets or remove system offsets. A 16-bit serial interface is provided, interfacing easily to most DSPs. The receive path also provides a means to vary the sampling instant, giving a resolution to 1/32 of a symbol interval. The auxiliary section provides two 8-bit DACs and one 10-bit DAC for functions such as automatic gain control (AGC), automatic frequency control (AFC) and power amplifier control. As it is a necessity for all digital mobile systems to use the lowest possible power, the device has receive and auxiliary power down options. The AD7013 is housed in a space efficient 28-pin SSOP (Shrink Small Outline Package). FUNCTIONAL BLOCK DIAGRAM MCLK DGND VDD AUX DAC1 AUX DAC2 AUX DAC3 FS ADJUST VAA AGND DxCLK DATA IN FRAME IN MODE1 FRAME OUT SERIAL INTERFACE 10-BIT AUX DAC 8-BIT AUX DAC 8-BIT AUX DAC FULL-SCALE ADJUST AGND AGND LATCH LATCH LATCH AD7013 1.23V REFERENCE ANALOG MODE FIR DIGITAL FILTER ROOT RAISED COSINE FIR DIGITAL FILTER BYPASS IRx ∆Σ–∆ MODULATOR SWITCHED CAP FILTER IRx MUX AUX IRx AUX IRx QRx OFFSET ADJUST ANALOG MODE FIR DIGITAL FILTER ROOT RAISED COSINE FIR DIGITAL FILTER ∆Σ–∆ MODULATOR SWITCHED CAP FILTER QRx MUX AUX QRx AUX QRx Rx CLK RECEIVE CHANNEL SERIAL INTERFACE OFFSET ADJUST Rx DATA Rx FRAME REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 AD7013–SPECIFICATIONS Parameter RECEIVE SECTION ADC SPECIFICATION Number of Input Channels 4 1 (VAA = VDD = +5 V ± 10%; AGND = DGND = 0 V; fMCLK = 6.2208 MHz; TA = TMIN to TMAX, unless otherwise noted) Units Test Conditions/Comments AD7013A (IRx–IRx) and QRx–QRx); CR12 = 0 (AUX IRx–AUX IRx) and (AUX QRx–AUX QRx); CR12 = 1 Bits Volts p-p Volts Volts Volts min/max Volts min/max % mV mV Number of ADC Channels Resolution ADC Signal Range Differential Signal Range Single-Ended Signal Range VBIAS Input Range Accuracy Accuracy Bias Offset Error 2 15 2.6 VBIAS ± 0.65 VBIAS ± 1.3 0.65 to (VAA–0.65) 1.3 to (VAA–1.3) ± 7.5 ± 7.5 ± 55 Measured Using an Input Sine Wave of 3 kHz For Both Noninverting and Inverting Analog Inputs For Noninverting Analog Inputs; Inverting Analog Inputs = VBIAS Differential Single-Ended Autocalibration; VBIAS = min/max User Calibration; I & Q Offset Adjust Registers Equal to Zero Measured Using an Input Sine Wave of 3 kHz with Both Noninverting and Inverting Inputs Tied Together Digital Mode Filter; CR11 = 0 Analog Mode Filter; CR11 = 1 Digital Mode Filter; CR11 = 0 Analog Mode Filter; CR11 = 1 MCLK = 6.2208 MHz/5.12 MHz; MCLK/4 MCLK = 6.2208 MHz/5.12 MHz; 4 × Sampling of the Symbol Rate, MCLK/64 MCLK = 6.2208 MHz/5.12 MHz; 2 × Sampling of the Symbol Rate, MCLK/128 MCLK = 6.2208 MHz Dynamic Specifications CMRR –40 dB typ Dynamic Range SNR2 Input Sampling Rate Output Word Rate 70 65 65 68 60 63 1.5552/1.28 97.2/80 48.6/40 dB typ dB typ dB min dB typ dB min dB typ MHz kHz kHz RECEIVE DIGITAL FILTERS Digital Mode Root-Raised-Cosine Settling Time Absolute Group Delay Frequency Response 0–7.8975 kHz 11.9 kHz 16.4025 kHz > 30 kHz Analog Mode Brick Wall Filter Settling Time Absolute Group Delay Frequency Response 0–8 kHz 11.4 kHz 15 kHz >17 kHz α = 0.35 329.2 164.6 ±.


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