71V016SA 16-Bit Datasheet

71V016SA Datasheet, PDF, Equivalent


Part Number

71V016SA

Description

3.3V CMOS Static RAM 1 Meg (64K x 16-Bit)

Manufacture

Integrated Device Technology

Total Page 9 Pages
Datasheet
Download 71V016SA Datasheet


71V016SA
3.3V CMOS Static RAM
1 Meg (64K x 16-Bit)
IDT71V016SA
Features
x 64K x 16 advanced high-speed CMOS Static RAM
x Equal access and cycle times
— Commercial: 10/12/15/20ns
— Industrial: 12/15/20ns
x One Chip Select plus one Output Enable pin
x Bidirectional data inputs and outputs directly
LVTTL-compatible
x Low power consumption via chip deselect
x Upper and Lower Byte Enable Pins
x Single 3.3V power supply
x Available in 44-pin Plastic SOJ, 44-pin TSOP, and
48-Ball Plastic FBGA packages
Functional Block Diagram
Output
OE Enable
Buffer
Description
The IDT71V016 is a 1,048,576-bit high-speed Static RAM organized
as 64K x 16. It is fabricated using IDT’s high-perfomance, high-reliability
CMOS technology. This state-of-the-art technology, combined with inno-
vative circuit design techniques, provides a cost-effective solution for high-
speed memory needs.
The IDT71V016 has an output enable pin which operates as fast
as 5ns, with address access times as fast as 10ns. All bidirectional
inputs and outputs of the IDT71V016 are LVTTL-compatible and operation
is from a single 3.3V supply. Fully static asynchronous circuitry is used,
requiring no clocks or refresh for operation.
The IDT71V016 is packaged in a JEDEC standard 44-pin Plastic
SOJ, a 44-pin TSOP Type II, and a 48-ball plastic 7 x 7 mm FBGA.
A0 – A15
Address
Buffers
Chip
CS Enable
Buffer
Write
WE Enable
Buffer
BHE
BLE
Byte
Enable
Buffers
©2000 Integrated Device Technology, Inc.
Row / Column
Decoders
64K x 16
Memory
Array
8
Sense
16 Amps
and
Write
Drivers
8
High
Byte
I/O
Buffer
Low
Byte
I/O
Buffer
I/O15
8
I/O8
I/O7
8
I/O0
3834 drw 01
JUNE 2002
1
DSC-3834/06

71V016SA
IDT71V016SA, 3.3V CMOS Static RAM
1 Meg (64K x 16-Bit)
Pin Configurations
A4
A3
A2
A1
A0
CS
I/O0
I/O1
I/O2
I/O3
VDD
VSS
I/O4
I/O5
I/O6
I/O7
WE
A15
A14
A13
A12
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
SO44-1
SO44-2
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
BHE
BLE
I/O15
I/O14
I/O13
I/O12
VSS
VDD
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
SOJ/TSOP
Top View
3834 drw 02
Truth Table(1)
CS OE WE BLE BHE
HX X
LLH
LLH
LLH
LX L
LX L
LX L
LHH
LXX
X
L
H
L
L
L
H
X
H
X
H
L
L
L
H
L
X
H
NOTE:
1. H = VIH, L = VIL, X = Don't care.
Commercial and Industrial Temperature Ranges
12 3 4 5 6
A BLE
OE
A0
A1
A2
NC
B I/O8
BHE
A3
A4
CS I/O0
C I/O9
I/O10
A5
A6 I/O1 I/O2
D VSS
I/O11
NC
A7
I/O3 VDD
E VDD
I/O12
NC
NC
I/O4 VSS
F I/O14
I/O13
A14
A15
I/O5 I/O6
G I/O15
NC
A12
A13
WE
I/O7
H NC
A8
A9 A10
FBGA (BF48-1)
Top View
Pin Description
A0 – A15
Address Inputs
CS Chip Select
WE Write Enable
OE Output Enable
BHE High Byte Enable
BLE Low Byte Enable
I/O0 – I/O15
Data Input/Output
VDD 3.3V Power
VSS Ground
A11 NC
3834 tbl 02a
Input
Input
Input
Input
Input
Input
I/O
Power
Gnd
3834 tbl 01
I/O0-I/O7
High-Z
DATAOUT
High-Z
DATAOUT
DATAIN
DATAIN
High-Z
High-Z
High-Z
I/O8-I/O15
High-Z
High-Z
DATAOUT
DATAOUT
DATAIN
High-Z
DATAIN
High-Z
High-Z
Function
Deselected – Standby
Low Byte Read
High Byte Read
Word Read
Word Write
Low Byte Write
High Byte Write
Outputs Disabled
Outputs Disabled
3834 tbl 02
6.422


Features 3.3V CMOS Static RAM 1 Meg (64K x 16-Bit ) Features x x IDT71V016SA Descriptio n The IDT71V016 is a 1,048,576-bit high -speed Static RAM organized as 64K x 16 . It is fabricated using IDT’s high-p erfomance, high-reliability CMOS techno logy. This state-of-the-art technology, combined with innovative circuit desig n techniques, provides a cost-effective solution for highspeed memory needs. T he IDT71V016 has an output enable pin w hich operates as fast as 5ns, with addr ess access times as fast as 10ns. All b idirectional inputs and outputs of the IDT71V016 are LVTTL-compatible and oper ation is from a single 3.3V supply. Ful ly static asynchronous circuitry is use d, requiring no clocks or refresh for o peration. The IDT71V016 is packaged in a JEDEC standard 44-pin Plastic SOJ, a 44-pin TSOP Type II, and a 48-ball plas tic 7 x 7 mm FBGA. x x x x x x 64K x 16 advanced high-speed CMOS Static RAM Equal access and cycle times — Comme rcial: 10/12/15/20ns — Industrial: 12/15/20ns One Chip Select plus .
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