73M2910L Microcontroller Datasheet

73M2910L Datasheet, PDF, Equivalent


Part Number

73M2910L

Description

Microcontroller

Manufacture

ETC

Total Page 30 Pages
Datasheet
Download 73M2910L Datasheet


73M2910L
DESCRIPTION
The 73M2910L high performance micro-controller is
based on the industry standard 8-bit 8032
implemented in an advanced submicron CMOS
process. The processor has the attributes of the
8032, including instruction cycle time, UART, timers,
interrupts, 256 bytes of on-chip RAM and
programmable I/O. The architecture has been
optimized for low power portable modem or
communication applications by integrating unique
features with the core CPU.
A key feature is a user friendly HDLC Packetizer,
accessed through the special function registers. It
has a serial I/O, hardware support for 16 and 32-bit
CRC, zero insert/delete control, a dedicated interrupt
and a clear channel mode for by-passing the
packetizer.
Other features include additional user programmable
I/O with programmable bank select and chip select
logic, designed to eliminate board level glue logic. It
also includes two general-purpose input ports with
programmable wakeup capability.
For devices that require non-multiplexed address
and data buses, eight latched outputs for the low
byte of the address are available.
(continued)
BLOCK DIAGRAM
73M2910L
Microcontroller
April 2000
FEATURES
8032 compatible instruction set
44 MHz Operation from 3.3 to 5.5V
HDLC support logic (Packetizer, 16 and 32
CRC, zero ID)
24 pins for user programmable I/O ports
8 pins programmable chip select logic or I/O
for memory mapped peripheral eliminating
glue logic
3 external interrupt sources (programmable
polarity)
16 dedicated latched address pins
Multiplexed data/address bus
Instruction cycle time identical to 8032
Buffered oscillator (or OSC/2) output pin
1.8432 MHz UART clock available
Bank select circuitry to support up to 128k of
external program memory
Also available in 100-Lead QFP and 100-Pin
PGA packages
(2:0)
INTERRUPT
CONTROL
USR 1.0
USR 1.1
USR 1.2
USR 1.3
TIMERS
RXD
TXD
PTXCLK
PTXD
PRXCLK
PRXD
UART
HDLC
TIME GEN
CPU
SFR BUS
RAM 256 X 8
ALE
MEM I/O CTRL
A (15:0)
D (7:0)
USR I/O
USR5 (1:0)
CSB (7:0)
USR3 (7:0)
USR I/O
USR2 (7:0)
USR1 (7:0)

73M2910L
73M2910L
Microcontroller
DESCRIPTION (continued)
The 73M2910L has two extra interrupt sources, an
external interrupt and a HDLC interrupt. The HDLC
interrupt has two registers associated with it; the
HDLC Interrupt Register which is used to determine
the source of the interrupt, and the HDLC Interrupt
Enable Register that enables the source of the
interrupt.
The state of the external interrupts can be read
through a register allowing the interrupt pins to be
used as inputs. The interrupt pins INT0 and INT1
can be either negative edge, positive edge or level
triggered. The INT2 pin is always edge triggered.
Two buffered clock outputs have been added to
support peripheral functions such as UARTs,
modems and other clocked devices. The main
internal processor clock frequency can be divided by
2 for power conservation in functional modes that
only require half the clock speed.
Additional internal special function registers are
used for firmware control over the HDLC Packetizer,
the clocks and the programmable I/O ports.
To accommodate processor peripherals when
operating at higher frequencies, the processor’s
timing has been altered to allow more address setup
time for slower peripheral program ROM and
memory mapped peripherals.
For low power applications the 73M2910L supports
two power conservation modes: idle and power-down.
In the power-down state the total current consumption
is less than 10 µA at room temperature.
DEVELOPER’S NOTE:
The 73M2910L is also available in a
100-Pin PGA package for system developers. The
PGA package is more convenient and reliable for
development emulation systems than the other
package styles. Emulation systems for the
73M2910L are available through Signum Systems,
11992 Challenger Court, Moorpark, CA 93021
(805) 523-9774.
8032 REFERENCE
This Document will describe the features unique to
the 73M2910L. Please refer to a 8032 Programmer’s
Guide, Architectural Overview and Hardware
Description for details on the instruction set, timers,
UART, interrupt control, and memory structure.
2


Features 73M2910L Microcontroller April 2000 DES CRIPTION The 73M2910L high performance micro-controller is based on the indust ry standard 8-bit 8032 implemented in a n advanced submicron CMOS process. The processor has the attributes of the 803 2, including instruction cycle time, UA RT, timers, interrupts, 256 bytes of on -chip RAM and programmable I/O. The arc hitecture has been optimized for low po wer portable modem or communication app lications by integrating unique feature s with the core CPU. A key feature is a user friendly HDLC Packetizer, accesse d through the special function register s. It has a serial I/O, hardware suppor t for 16 and 32-bit CRC, zero insert/de lete control, a dedicated interrupt and a clear channel mode for by-passing th e packetizer. Other features include ad ditional user programmable I/O with pro grammable bank select and chip select l ogic, designed to eliminate board level glue logic. It also includes two gener al-purpose input ports with programmable wakeup capability. For.
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