74107 FLOP Datasheet

74107 Datasheet, PDF, Equivalent


Part Number

74107

Description

DUAL J-K FLIP FLOP

Manufacture

STMicroelectronics

Total Page 11 Pages
Datasheet
Download 74107 Datasheet


74107
M54HC107
M74HC107
DUAL J-K FLIP FLOP WITH CLEAR
. HIGH SPEED
fMAX = 75 MHz (TYP.) AT VCC = 5 V
. LOW POWER DISSIPATION
ICC = 2 µA (MAX.) AT TA = 25 °C
. HIGH NOISE IMMUNITY
VNIH = VNIL = 28 % VCC (MIN.)
. OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
. SYMMETRICAL OUTPUT IMPEDANCE
IOH= IOL = 4 mA (MIN.)
. BALANCED PROPAGATION DELAYS
tPLH = tPHL
. WIDE OPERATING VOLTAGE RANGE
VCC (OPR) = 2 V TO 6 V
. PIN AND FUNCTION COMPATIBLE WITH
54/74LS107
B1R
(Plastic Package)
F1R
(Ceramic Package)
M 1R
(Micro Package)
C1R
(Chip Carrier)
ORDER CODES :
M 54HC 10 7F 1R
M 74H C1 07 M1 R
M 74HC 10 7B 1R
M 74H C1 07 C1 R
DESCRIPTION
The M54/74HC107 is a high speed CMOS DUAL J-
K FLIP FLOP fabricated in silicon gate C2MOS tech-
nology. It has the same high speed performance of
LSTTL combined with true CMOS low power con-
sumption. These flip-flop are edge sensitive to the
clock input and change state on the negative going
transition of the clock pulse. Each one has inde-
pendent J, K, CLOCK, and CLEAR input and Q and
Q outputs. CLEAR is independent of the clock and
accomplished by a logic low on the input. All inputs
are equipped with protection circuits against static
discharge and transient excess voltage.
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN CONNECTIONS (top view)
October 1992
NC =
No Internal
Connection
1/11

74107
M54/M74HC107
TRUTH TABLE
CLR
L
H
H
H
H
H
X: Don’t Care
INPUTS
JK
XX
LL
LH
HL
HH
XX
CK
X
PIN DESCRIPTION
PIN No
1, 8, 4, 11
2, 6
3, 5
12, 9
13, 10
7
14
SYMBOL
1J, 2J, 1K,
2K
1Q, 2Q
1Q, 2Q
1CK, 2CK
1CLR,
2CLR
GND
VCC
NAME AND FUNCTION
Synchronous Inputs;
Flip-Flop 1 And 2
Complement Flip-Flop
Outputs
True Flip-Flop Outputs
Clock Input
Asynchronous Reset
Inputs
Ground (0V)
Positive Supply Voltage
OUTPUTS
QQ
LH
Qn Qn
LH
HL
Qn Qn
Qn Qn
IEC LOGIC SYMBOL
FUNCTION
CLEAR
NO CHANGE
TOGGLE
NO CHANGE
LOGIC DIAGRAM (1/2 Package)
2/11


Features M54HC107 M74HC107 DUAL J-K FLIP FLOP WIT H CLEAR . . . . . . . . HIGH SPEED fM AX = 75 MHz (TYP.) AT VCC = 5 V LOW POW ER DISSIPATION ICC = 2 µA (MAX.) AT TA = 25 °C HIGH NOISE IMMUNITY VNIH = VN IL = 28 % VCC (MIN.) OUTPUT DRIVE CAPAB ILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE IOH = IOL = 4 mA (MIN. ) BALANCED PROPAGATION DELAYS tPLH = tP HL WIDE OPERATING VOLTAGE RANGE VCC (OP R) = 2 V TO 6 V PIN AND FUNCTION COMPAT IBLE WITH 54/74LS107 B1R (Plastic Pack age) F1R (Ceramic Package) M1R (Micro Package) C1R (Chip Carrier) ORDER CO DES : M54HC107F1R M74HC107M1R M74HC107B 1R M74HC107C1R DESCRIPTION The M54/74H C107 is a high speed CMOS DUAL JK FLIP FLOP fabricated in silicon gate C2MOS t echnology. It has the same high speed p erformance of LSTTL combined with true CMOS low power consumption. These flip- flop are edge sensitive to the clock in put and change state on the negative go ing transition of the clock pulse. Each one has independent J, K, CLOCK, and CLEAR input and Q and Q outputs.
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